AT94K05AL-25BQU Atmel, AT94K05AL-25BQU Datasheet - Page 130

• Manufacturer Part Number: AT94K05AL-25BQU
• Description: IC FPSLIC 5K GATE 25MHZ 144-LQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25BQU

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

130
AT94KAL Series FPSLIC
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Regis-
ter, UDRn. Data is transferred from UDRn to the Transmit shift register when:
If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDRn to the shift reg-
ister. At this time the UDREn (UART Data Register Empty) bit in the UART Control and Status
Register, UCSRnA, is set. When this bit is set (one), the UART is ready to receive the next char-
acter. At the same time as the data is transferred from UDRn to the 10(11)-bit shift register, bit 0
of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If a 9-bit data word is
selected (the CHR9n bit in the UART Control and Status Register, UCSRnB is set), the TXB8 bit
in UCSRnB is transferred to bit 9 in the Transmit shift register.
On the Baud-rate clock following the transfer operation to the shift register, the start bit is shifted
out on the TXDn pin. Then follows the data, LSB first. When the stop bit has been shifted out,
the shift register is loaded if any new data has been written to the UDRn during the transmission.
During loading, UDREn is set. If there is no new data in the UDRn register to send when the stop
bit is shifted out, the UDREn flag will remain set until UDRn is written again. When no new data
has been written, and the stop bit has been present on TXDn for one bit length, the TX Complete
flag, TXCn, in UCSRnA is set.
The TXENn bit in UCSRnB enables the UART transmitter when set (one). When this bit is
cleared (zero), the PE0 (UART0) or PE2 (UART1) pin can be used for general I/O. When TXENn
is set, the UART Transmitter will be connected to PE0 (UART0) or PE2 (UART1), which is
forced to be an output pin regardless of the setting of the DDE0 bit in DDRE (UART0) or DDE2
in DDRE (UART1).
• A new character has been written to UDRn after the stop bit from the previous character has
• A new character has been written to UDRn before the stop bit from the previous character
been shifted out. The shift register is loaded immediately.
has been shifted out. The shift register is loaded when the stop bit of the character currently
being transmitted has been shifted out.
1138I–FPSLI–1/08