AT94K05AL-25BQU Atmel, AT94K05AL-25BQU Datasheet - Page 149

IC FPSLIC 5K GATE 25MHZ 144-LQFP

AT94K05AL-25BQU

Manufacturer Part Number
AT94K05AL-25BQU
Description
IC FPSLIC 5K GATE 25MHZ 144-LQFP
Manufacturer
Atmel
Series
FPSLIC®r
Datasheet

Specifications of AT94K05AL-25BQU

Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
4K-16K
Fpga Sram
2kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
256
Fpga Gates
5K
Fpga Registers
436
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT94K05AL-25BQU
Manufacturer:
Atmel
Quantity:
10 000
Table 4-29.
1138I–FPSLI–1/08
(TWSR)
Status
Code
$08
$10
$18
$20
$28
$30
$38
Serial Bus and 2-wire
A START condition
has been transmitted
A repeated START
condition has been
transmitted
SLA+W has been
transmitted;
ACK has been
received
SLA+W has been
transmitted;
NOT ACK has been
received
Data byte has been
transmitted;
ACK has been
received
Data byte has been
transmitted;
NOT ACK has been
received
Arbitration lost in
SLA+W or data bytes
Status of the 2-wire
Serial Hardware
Status Codes for Master Transmitter Mode
Load SLA+W
Load SLA+W or
Load SLA+R
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
To/From TWDR
Application Software Response
STA
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
STO
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
To TWCR
TWINT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AT94KAL Series FPSLIC
TWEA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to Master Receiver mode
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO flag will be reset
STOP condition followed by a START
condition will be transmitted and TWSTO flag
will be reset
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO flag will be reset
STOP condition followed by a START
condition will be transmitted and TWSTO flag
will be reset
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO flag will be reset
STOP condition followed by a START
condition will be transmitted and TWSTO flag
will be reset
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO flag will be reset
STOP condition followed by a START
condition will be transmitted and TWSTO flag
will be reset
2-wire serial bus will be released and not
addressed Slave mode entered
A START condition will be transmitted when
the bus becomes free
Next Action Taken by 2-wire
Serial Hardware
149

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