AT94K05AL-25BQU Atmel, AT94K05AL-25BQU Datasheet - Page 60

• Manufacturer Part Number: AT94K05AL-25BQU
• Description: IC FPSLIC 5K GATE 25MHZ 144-LQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25BQU

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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60
Reset and Interrupt Handling
AT94KAL Series FPSLIC
• Bits 3..0 - FINT11 - 8: FPGA Interrupt Masks 11 - 8
See Bits 3..0 - FINT3 - 0: FPGA Interrupt Masks 3 - 0. Not available on the AT94K05.
• Bits 3..0 - FINT15 - 12: FPGA Interrupt Masks 15 -12
See Bits 3..0 - FINT3 - 0: FPGA Interrupt Masks 3 - 0. Not available on the AT94K05.
The embedded AVR and FPGA core provide 35 different interrupt sources. These interrupts and
the separate reset vector each have a separate program vector in the program memory space.
All interrupts are assigned individual enable bits (masks) which must be set (one) together with
the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space must be defined as the Reset and Interrupt
vectors. The complete list of vectors is shown in
levels of the different interrupts. The lower the address the higher the priority level. RESET has
the highest priority, and next is FPGA_INT0 – the FPGA Interrupt Request 0 etc.
Table 4-6.
Vector No.
(hex)
0A
0B
0C
0D
0E
0F
01
02
03
04
05
06
07
08
09
10
Reset and Interrupt Vectors
Program
Address
$000A
$000C
$000E
$001A
$001C
$001E
$0000
$0002
$0004
$0006
$0008
$0010
$0012
$0014
$0016
$0018
Source
RESET
FPGA_INT0
EXT_INT0
FPGA_INT1
EXT_INT1
FPGA_INT2
EXT_INT2
FPGA_INT3
EXT_INT3
TIM2_COMP
TIM2_OVF
TIM1_CAPT
TIM1_COMPA
TIM1_COMPB
TIM1_OVF
TIM0_COMP
Table
Interrupt Definition
Reset Handle: Program
Execution Starts Here
FPGA Interrupt0 Handle
External Interrupt0 Handle
FPGA Interrupt1 Handle
External Interrupt1 Handle
FPGA Interrupt2 Handle
External Interrupt2 Handle
FPGA Interrupt3 Handle
External Interrupt3 Handle
Timer/Counter2 Compare
Match Interrupt Handle
Timer/Counter2 Overflow
Interrupt Handle
Timer/Counter1 Capture
Event Interrupt Handle
Timer/Counter1 Compare
Match A Interrupt Handle
Timer/Counter1 Compare
Match B Interrupt Handle
Timer/Counter1 Overflow
Interrupt Handle
Timer/Counter0 Compare
Match Interrupt Handle
4-6. The list also determines the priority
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