XE8801AMI000WP Semtech, XE8801AMI000WP Datasheet - Page 128

• Manufacturer Part Number: XE8801AMI000WP
• Description: SENSING MACHINE WITH 16 + 10 BIT
• Manufacturer: Semtech

Specifications of XE8801AMI000WP

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 512 x 8
• Interface: UART, USRT
• Number Of I /o: 24
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: Die
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Other names: Q2722595

When the capture function is active, the A and B counters must be written with the value 0xFF and can either
upcount or downcount. They do count circularly: they restart at zero or at the maximal value (either 0xFF when not
cascaded or 0xFFFF when cascaded) when respectively an overflow or an underflow condition occurs in the
counting.
CapFunc(1:0) in register RegCntConfig2 determines if the capture function is enabled or not and selects which
edges of the capture signal source are valid for the capture operation. The source of the capture signal can be
selected by setting CapSel(1:0) in the RegCntConfig2 register. For all sources, rising, falling or both edge
sensitivity can be selected. Table 18-14 shows the capture condition as a function of the setting of these
configuration bits.
CapFunc(1:0) and CapSel(1:0) can be modified only when the counters are stopped otherwise data may be
corrupted during one counter clock cycle.
Due to the synchronization mechanism of the shadow registers and depending on the frequency ratio between the
capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the
effective capture condition occurred. When the counters A and B are not cascaded and do not operate on the
same clock, the interruptions on IrqA and IrqB which inform that the capture condition was met, may appear at
different moments. In this case, the processor should read the shadow register associated to a counter only if the
interruption related to this counter has been detected.
It must be noted that when counters A and B are cascaded, the capture might happen at different cycles for the A
and B registers. This is due to the asynchronous relationship between counter and capture clock and to the fact
that the capture condition detection is independent for A and B counters.
© Semtech 2005
CapSel(1:0)
11
10
01
00
Selected capture signal
32 K
PA3
PA2
1 K
Table 18-14: Capture condition selection
CapFunc
18-10
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Selected condition
XE8801A – SX8801R
-
1 K rising edge
1 K falling edge
1 K both edges
-
32 K rising edge
32 K falling edge
32 K both edges
-
PA3 rising edge
PA3 falling edge
PA3 both edges
-
PA2 rising edge
PA2 falling edge
PA2 both edges
Capture condition
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