XE8801AMI000WP Semtech, XE8801AMI000WP Datasheet - Page 21

• Manufacturer Part Number: XE8801AMI000WP
• Description: SENSING MACHINE WITH 16 + 10 BIT
• Manufacturer: Semtech

Specifications of XE8801AMI000WP

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 512 x 8
• Interface: UART, USRT
• Number Of I /o: 24
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: Die
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Other names: Q2722595

3.3
Table 3-4 shows a short description of the different instructions available on the Coolrisc816. The notation
conditional jump instruction refers to the condition description as given in Table 3-6. The notation
reg3
extended address modes as defined in Table 3-5. The notation DM(xxx) refers to the data memory location with
address xxx.
Instruction
Jump addr[15:0]
Jump ip
Jcc
Jcc
Call addr[15:0]
Call ip
Calls addr[15:0]
Calls ip
Ret
Rets
Reti
Push
Pop
Move reg,#data[7:0]
Move reg1,
Move reg,
Move eaddr,
Move addr[7:0],#data[7:0]
Cmvd reg1,
Cmvd reg,
Cmvs reg1,
Cmvs reg,
Shl reg1,
Shl
Shl reg,
Shlc reg1,
Shlc
Shlc reg,
Shr reg1,
Shr
Shr reg,
Shrc reg1,
Shrc
Shrc reg,
Shra reg1,
Shra
Shra reg,
Cpl1 reg1,
Cpl1
Cpl1 reg,
Cpl2 reg1,
Cpl2
Cpl2 reg,
Cpl2c reg1,
Cpl2c
Cpl2c reg,
Inc reg1,
Inc
Inc reg,
Incc reg1,
Incc
Incc reg,
© Semtech 2005
reg
reg
addr[15:0]
ip
reg
reg
reg
reg
reg
reg
reg
refers to one of the CPU internal registers of Table 3-1. The notation
reg
eaddr
eaddr
eaddr
reg2
eaddr
CPU instruction short reference
reg2
eaddr
reg2
eaddr
eaddr
eaddr
eaddr
eaddr
reg2
eaddr
reg2
reg2
reg2
eaddr
eaddr
reg2
reg2
reg2
reg2
reg2
reg2
reg
Modification
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-,-, -
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
-,-,-, -
Operation
PC := addr[15:0]
PC := ip
if
if
ST
ST
ip := PC+1; PC := addr[15:0]
ip := PC+1; PC := ip
PC := ST
PC := ip
PC := ST
PC := PC+1; ST
PC := PC+1; ip := ST
a := data[7:0];
a := reg2;
a := DM(eaddr);
DM(eaddr)
DM(addr[7:0]) := data[7:0]
a := reg2; if C=0 then
a := DM(eaddr); if C=0 then
a := reg2; if C=1 then
a := DM(eaddr); if C=1 then
a := reg2<<1; a[0] := 0; C := reg2[7];
a := reg<<1; a[0] := 0; C := reg[7];
a := DM(eaddr)<<1; a[0] :=0; C := DM(eaddr)[7];
a := reg2<<1; a[0] := C; C := reg2[7];
a := reg<<1; a[0] := C; C := reg[7];
a := DM(eaddr)<<1; a[0] := C; C := DM(eaddr)[7];
a := reg2>>1; a[7] := 0; C := reg2[0];
a := reg>>1; a[7] := 0; C := reg[0];
a := DM(eaddr)>>1; a[7] := 0; C := DM(eaddr)[0];
a := reg2>>1; a[7] := C; C := reg2[0];
a := reg>>1; a[7] := C; C := reg[0];
a := DM(eaddr)>>1; a[7] := C; C := DM(eaddr)[0];
a := reg2>>1; a[7] := reg2[7]; C := reg2[0];
a := reg>>1; a[7] := reg[7]; C := reg[0];
a := DM(eaddr)>>1; a[7] := DM(eaddr)[7]; C := DM(eaddr)[0];
a := NOT(reg2);
a := NOT(reg);
a := NOT(DM(eaddr));
a := NOT(reg2)+1; if a=0 then C:=1 else C := 0;
a := NOT(reg)+1; if a=0 then C:=1 else C := 0;
a := NOT(DM(eaddr))+1; if a=0 then C:=1 else C := 0;
a := NOT(reg2)+C; if a=0 and C=1 then C:=1 else C := 0;
a := NOT(reg)+C; if a=0 and C=1 then C:=1 else C := 0;
a := NOT(DM(eaddr))+C; if a=0 and C=1 then C:=1 else C := 0;
a := reg2+1; if a=0 then C := 1 else C := 0;
a := reg+1; if a=0 then C := 1 else C := 0;
a := DM(eaadr)+1; if a=0 then C := 1 else C := 0;
a := reg2+C; if a=0 and C=1 then C := 1 else C := 0;
a := reg+C; if a=0 and C=1 then C := 1 else C := 0;
a := DM(eaadr)+C; if a=0 and C=1 then C := 1 else C := 0;
cc
cc
n+1
n+1
is true then PC := addr[15:0]
is true then PC := ip
:= ST
:= ST
1
1
; ST
; ST
reg1
n
n
:=
(n>1); ST
(n>1); ST
reg
n
n
reg
:=
reg
:= ST
:= ST
n+1
reg
reg1
reg2
:= data[7:0]
:= ST
:= a
3-4
:=
n+1
n+1
1
:= a
reg1
reg1
; ST
1
1
reg
DM(eaddr)
:= PC+1; PC := addr[15:0]
:= PC+1; PC := ip
(n>1)
(n>1); GIE :=1
n
(n>1); ST
n
:= a
:= a;
:= a;
:= ST
reg
reg
:= a
:= a
n+1
reg
reg
reg
reg
1
(n>1)
reg1
reg1
:= ip
reg1
reg1
:= a
:= a
:= a
:= a
reg
reg
:= a
:=a
:= a
:= a
reg1
:= a
reg1
eaddr
:= a
reg
:= a
reg1
:= a
reg
reg
reg
reg
reg
:= a
reg
and
:= a
reg1
:= a
:= a
:= a
:= a
:= a
reg
XE8801A – SX8801R
:= a
reg
DM(eaddr)
reg1
:= a
:= a
reg
:= a
reg
:= a
:= a
reg
:= a
:= a
refer to one of the
www.semtech.com
reg, reg1, reg2,
cc
in the