XE8801AMI000WP Semtech, XE8801AMI000WP Datasheet - Page 63

• Manufacturer Part Number: XE8801AMI000WP
• Description: SENSING MACHINE WITH 16 + 10 BIT
• Manufacturer: Semtech

Specifications of XE8801AMI000WP

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 512 x 8
• Interface: UART, USRT
• Number Of I /o: 24
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: Die
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Other names: Q2722595

Port A as an event source:
The interrupt signals of the pins PA[0] and PA[1] are also available as events on the event controller.
PortA as a clock source (product dependent):
Images of the PA[0] to PA[3] input ports (debounced or not) are available as clock sources for the
counter/timer/PWM peripheral (see the counter block documentation for more information).
Port A as a reset source:
Port A can be used to generate a system reset by placing a predetermined word on Port A externally. The reset is
built using a logical and of the 8 PARes[x] signals:
PAReset[x] is itself a logical function of the corresponding pin PA[x]. One of four logical functions can be selected
for each pin by writing into two registers RegPARes0 and RegPARes1 as shown in Table 11-8.
A reset from Port A can be inhibited by placing a 0 on both PARes1[x] and PARes0[x] for at least 1 pin. Setting
both PARes1[x] and PARes0[x] to 1, makes the reset independent of the value on the corresponding pin. Setting
both registers to hFF, will reset the circuit independent from the Port A input value. This makes it possible to do a
reset by software.
Note: depending of the value of PA[0] to PA[7], the change of RegPARes0 and RegPARes1 can cause a reset.
Therefore it is safe to have always one (RegPARes0[x], RegPARes1[x]) equal to ‘00’ during the setting operations.
Port A as a RC enable:
PA[0] can be used to enable the RC oscillator. When RCOnPA0 bit in RegSysMisc is set to 1 and the value of
PA[0] (debounced or not) is equal to 1, the EnRc bit in RegSysClock is automatically set to 1.
11.6 Port A electrical specification
Note 1: this value is indicative only since it depends on the package.
Table 11-9. Port A electrical specification.
© Semtech 2005
Sym
V
V
R
Cin
INL
INH
PU
description
Input high voltage
Input low voltage
Pull-up resistance
Input capacitance
resetfromportA = PAReset[7] AND PAReset[6] AND PAReset[5] AND ... AND PAReset[0]
PARes1[x]
Table 11-8: Selection bits for reset signal
0.7*VBAT
0
0
1
1
VSS
min
20
3.5
typ
50
PARes0[x]
11-5
0.2*VBAT
0
1
0
1
VBAT
max
80
unit Comments
kΩ
pF
V
V
PAReset[x]
not(PA[x])
PA[x]
0
1
VBAT≥2.4V
VBAT≥2.4V
Note 1
XE8801A – SX8801R
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