XE8801AMI000WP Semtech, XE8801AMI000WP Datasheet - Page 37

• Manufacturer Part Number: XE8801AMI000WP
• Description: SENSING MACHINE WITH 16 + 10 BIT
• Manufacturer: Semtech

Specifications of XE8801AMI000WP

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 512 x 8
• Interface: UART, USRT
• Number Of I /o: 24
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: Die
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Other names: Q2722595

Table 6-3. RegSysWD register
6.4 Reset handling capabilities
There are 5 reset sources:
Another reset source is the bit Sleep in the RegSysReset register. This source is fully controlled by software and
is only used during the sleep mode.
Four internal reset signals are generated from these sources and distributed through the system:
For
(2) For
Table 6-4 shows a summary of the dependency of the internal reset signals on the various reset sources. In all the
tables describing the different registers, the reset source is indicated.
Table 6-4 Internal reset assertion as a function of the reset source.
© Semtech 2005
7 – 4
Pos.
Asserted
reset source
POR
RESET pin (1)
RESET pin (2)
PortA input
Watchdog
BusError
Sleep
3
2
1
0
the circuits XE8801AM/XE88LC01AM/SX8801R and XE8805AM/XE88LC05AM
(1) For the circuits XE8801AM/XE88LC01AM/SX8801R and XE8805AM/XE88LC05AM
(2) For the circuits XE88LC01 and XE88LC05
the circuits XE88LC01 and XE88LC05
RegSysWD
-
WDKey[3]
WDCounter[3]
WDKey[2]
WDCounter[2]
WDKey[1]
WDCounter[1]
WDKey[0]
WDCounter[0]
• Power On Reset (POR)
• External reset from the RESET pin
• Programmable Port A input combination
• Programmable watchdog timer reset
• Programmable BusError reset on processor access outside the allocated memory map
• resetcold:
• resetsystem: is asserted when resetcold or any other enabled reset source is active
• resetpconf:
• resetsleep:
resetsystem
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
is asserted on POR
is asserted when resetsystem is active and if the
is set. This reset is generally used in the different ports. It allows to maintain the port
configuration unchanged while the rest of the circuit is reset.
is asserted when the circuit is in sleep mode
Rw
r
w
r
w
r
w
r
w
r
-
Reset
0000
0 resetcold
0 resetcold
0 resetcold
0 resetcold
EnResPConf=0
Asserted
Asserted
when
-
-
-
-
-
Function
unused
Watchdog Key bit 3
Watchdog counter bit 3
Watchdog Key bit 2
Watchdog counter bit 2
Watchdog Key bit 1
Watchdog counter bit 1
Watchdog Key bit 0
Watchdog counter bit 0
Internal reset signals
resetpconf
EnResPConf=1
6-3
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
when
-
EnResPConf bit in the
resetsleep
Asserted
Asserted
Asserted
-
-
-
-
XE8801A – SX8801R
resetcold
Asserted
Asserted
RegSysCtrl register
-
-
-
-
-
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