CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 21

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

10.0
The 12-bit timer operates with a 1- s tick, provides two interrupts (128 s and 1.024ms) and allows the firmware to directly time
events that are up to 4 ms in duration. The lower eight bits of the timer can be read directly by the firmware. Reading the lower
eight bits latches the upper four bits into a temporary register. When the firmware reads the upper four bits of the timer, it is actually
reading the count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even
when the two reads are separated in time.
Bit [7:0]: Timer lower eight bits.
Bit [3:0]: Timer higher nibble
Bit [7:4]: Reserved.
Document #: 38-08002 Rev. *B
Port 2 Interrupt Enable
Bit #
Bit Name
Read/Write
Reset
Port 3 Interrupt Enable
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Timer LSB
Bit #
Bit Name
Read/Write
Reset
Timer MSB
12-bit Free-Running Timer
Timer Bit 7
Reserved
Reserved
P0.7 Intr
Enable
W
W
7
0
7
0
R
7
0
7
–
0
TimerBit 6
Reserved
Reserved
P0.6 Intr
Enable
W
W
6
0
6
0
R
6
0
6
–
0
Timer Bit 5
Reserved
Figure 9-10. Port 3 Interrupt Enable
Reserved
P0.5 Intr
Figure 9-9. Port 2 Interrupt Enable
Enable
Figure 10-1. Timer LSB Register
W
W
R
Figure 10-2.
5
0
5
0
5
0
5
–
0
Timer Bit 4
Reserved
Reserved
P0.4 Intr
Enable
Timer MSB Register
W
W
R
4
0
4
0
4
0
4
–
0
Timer Bit 11 Timer Bit 10
Timer Bit 3
Reserved
P0.3 Intr
Enable
W
W
R
R
3
0
3
0
3
0
3
0
Timer Bit 2
Reserved
Reserved
W
W
R
R
2
0
2
0
2
0
2
0
Timer Bit 1
Timer Bit 9
Reserved
P3.1 Intr
Enable
W
W
R
R
1
0
1
0
1
0
1
0
CY7C65013
CY7C65113
Address 0x24
Address 0x25
Address 0x06
Address 0x07
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Timer Bit 0
Timer Bit 8
Reserved
P0.3 Intr
Enable
R
R
W
W
0
0
0
0
0
0
0
0