CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 24

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

Bit 6 : Continue/Busy
Bit 5 : Xmit Mode
Bit 4 : ACK
Bit 3 : Addr
Bit 2 : ARB Lost/Restart
Bit 1 : Receive Stop
Bit 0 : I
13.0
Bit 0: Run
Bit 1: Reserved
Bit 2: Interrupt Enable Sense
Document #: 38-08002 Rev. *B
Processor Status and Control
Bit #
Bit Name
Read/Write
Reset
microcontroller. If the chip is the target of an external master that wins arbitration, then the interrupt is held off until the
transaction from the external master is completed.
When MSTR Mode is cleared from 1 to 0 by a firmware write, an I
This bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin. In other words,
the bit has responded to an interrupt request and has completed the required update or read of the data register. During a
read this bit indicates if the hardware is busy and is locking out additional writes to the I
locking allows the hardware to complete certain operations that may require an extended period of time. Following an I
interrupt, the I
firmware to make one control register write without the need to check the Busy bit.
This bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. Clearing this bit
sets the part in receive mode. Firmware generally determines the value of this bit from the R/W bit associated with the I
address packet. The Xmit Mode bit state is ignored when initially writing the MSTR Mode or the Restart bits, as these cases
always cause transmit mode for the first byte.
This bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ACK signal
on the I
time. During transmits (Xmit Mode = 1), this bit should be cleared.
This bit is set by the I
The Addr bit is cleared when the firmware sets the Continue bit. This bit allows the firmware to recognize when the master
has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred.
This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along with the
Continue and MSTR Mode bits) to perform an I
to the data register before setting the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware
during the restart sequence.
This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive Stop bit is not set if the
firmware terminates the I
e.g., in receive mode if firmware sets the Continue bit and clears the ACK bit.
Set this bit to override GPIO definition with I
these pins are free to function as GPIOs. In I
of the GPIO configuration setting.
This bit is manipulated by the HALT instruction. When Halt is executed, all the bits of the Processor Status and Control
Register are cleared to 0. Since the run bit is cleared, the processor stops at the end of the current instruction. The processor
remains halted until an appropriate reset occurs (power-on or Watchdog). This bit should normally be written as a ‘1.’
Bit 1 is reserved and must be written as a zero.
2
C Enable
Processor Status and Control Register
2
C-compatible bus. Writing a 1 to this bit generates an ACK (SDA LOW) on the I2C-compatible bus at the ACK bit
Pending
IRQ
2
R
7
0
C-compatible block does not return to the Busy state until firmware sets the Continue bit. This allows the
2
C-compatible block during the first byte of a slave receive transaction, after an I
Watchdog
2
C transaction by not acknowledging the previous byte transmitted on the I
Reset
R/W
6
0
Figure 13-1. Processor Status and Control Register
USB Bus
Interrupt
Reset
R/W
2
5
0
C-compatible function on the two I
2
C-compatible mode, the two pins operate in open drain mode, independent
2
C restart sequence. The I
Power-on
Reset
R/W
1
4
2
C Stop bit is generated.
Suspend
R/W
3
0
2
C target address for the restart must be written
2
C-compatible pins. When this bit is cleared,
Interrupt
Enable
Sense
R
2
0
2
C Status and Control register. This
Reserved
R/W
1
0
2
C-compatible bus,
2
CY7C65013
CY7C65113
C start or restart.
Address 0xFF
Page 24 of 51
R/W
Run
0
1
2
2
C
C