CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 29

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

.
Refer to Sections 9.1 and 9.2 for more information of setting GPIO interrupt polarity and enabling individual GPIO interrupts. If
one port pin has triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive
(non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign interrupt priority
to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process.
14.8
The I
involves reading the I
I
subsequent transaction. The interrupt indicates that status bits are stable and it is safe to read and write the I
to Section 12.0 for details on the I
When enabled, the I
bits are in the I
The Continue/Busy bit is cleared by hardware prior to interrupt conditions 1 to 4. Once the Data Register has been read or written,
firmware should configure the other control bits and set the Continue/Busy bit for subsequent transactions. Following an interrupt
from master mode, firmware should perform only one write to the Status and Control Register that sets the Continue/Busy bit,
without checking the value of the Continue/Busy bit. The Busy bit may otherwise be active and I
changed by the hardware during the transaction, until the I
Document #: 38-08002 Rev. *B
2
1. In slave receive mode, after the slave receives a byte of data: The Addr bit is set, if this is the first byte since a start or restart
2. In slave receive mode, after a stop bit is detected: The Received Stop bit is set, if the stop bit follows a slave receive transaction
3. In slave transmit mode, after the slave transmits a byte of data: The ACK bit indicates if the master that requested the byte
4. In master transmit mode, after the master sends a byte of data. Firmware should load the Data Register if necessary, and
5. In master receive mode, after the master receives a byte of data: Firmware should read the data and set the ACK and
6. When the master loses arbitration: This condition clears the MSTR MODE bit and sets the ARB Lost/Restart bit immediately
C Data Register as appropriate, and finally writing the Processor Status and Control Register (Figure 13-1) to initiate the
GPIO
Pin
signal was sent by the external master. Firmware must read or write the data register as necessary, then set the ACK, Xmit
MODE, and Continue/Busy bits appropriately for the next byte.
where the ACK bit was cleared to 0, no stop bit detection occurs.
acknowledged the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then sets the
Xmit MODE and Continue/Busy bits as required.
set the Xmit MODE, MSTR MODE, and Continue/Busy bits appropriately. Clearing the MSTR MODE bit issues a stop signal
to the I
Continue/Busy bits appropriately for the next byte. Clearing the MSTR MODE bit at the same time causes the master state
machine to issue a stop signal to the I
and then waits for a stop signal on the I
IRA
2
C interrupt occurs after various events on the I
1 = Enable
0 = Disable
I
2
2
C Interrupt
C-compatible bus and return to the idle state.
2
C Status and Control Register.
2
C-compatible state machines generate interrupts on completion of the following conditions. The referenced
2
C Status and Control Register (Figure 12-2) to determine the cause of the interrupt, loading/reading the
Port Interrupt
Enable Register
2
Configuration
C registers.
Register
M
U
X
Port
2
C-compatible bus and leave the I2C-compatible hardware in the idle state.
2
C-compatible bus to generate the interrupt.
Figure 14-4. GPIO Interrupt Structure
1 = Enable
0 = Disable
2
C-compatible bus to signal the need for firmware interaction. This generally
2
(1 input per
C interrupt occurs.
GPIO pin)
OR Gate
(Bit 5, Register 0x20)
GPIO Interrupt
Global
Enable
1
GPIO Interrupt
Flip Flop
D
CLR
Q
2
C register contents may be
Interrupt
Encoder
Priority
2
CY7C65013
CY7C65113
C registers. Refer
Page 29 of 51
Interrupt
IRQout
Vector