CY7C67300-100AXE Cypress Semiconductor Corp, CY7C67300-100AXE Datasheet - Page 20

• Manufacturer Part Number: CY7C67300-100AXE
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXE

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Boost 3V OK (Bit 2)
The Boost 3V OK bit is a read only bit that returns the status of
the OTG Boost circuit.
1: Boost circuit not ok and internal voltage rails are below 3.0V
0: Boost circuit ok and internal voltage rails are at or above 3.0V
Sleep Enable (Bit 1)
Setting this bit to ‘1’ immediately initiates SLEEP mode. While in
SLEEP mode, the entire chip is paused, achieving the lowest
standby power state. All operations are paused, the internal
clock is stopped, the booster circuit and OTG VBUS charge
pump are all powered down, and the USB transceivers are
powered down. All counters and timers are paused but retain
their values; enabled PWM outputs freeze in their current states.
SLEEP mode exits by any activity selected in this register. When
SLEEP mode ends, instruction execution resumes within 0.5 ms.
1: Enable Sleep mode
0: No function
Interrupt Enable Register [0xC00E] [R/W]
Table 29. Interrupt Enable Register
Register Description
The Interrupt Enable register allows control of the hardware
interrupt vectors.
OTG Interrupt Enable (Bit 12)
The OTG Interrupt Enable bit enables or disables the OTG
ID/OTG4.4V Valid hardware interrupt.
1: Enable OTG interrupt
0: Disable OTG interrupt
SPI Interrupt Enable (Bit 11)
The SPI Interrupt Enable bit enables or disables the following
three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA
Block Done.
1: Enable SPI interrupt
0: Disable SPI interrupt
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Interrupt
Enable
HSS
R/W
15
0
7
0
-
In Mailbox
Reserved
Interrupt
Enable
R/W
14
0
6
0
-
Out Mailbox
Interrupt
Enable
R/W
13
0
5
0
-
Reserved
Interrupt
Enable
OTG
R/W
12
0
4
1
-
Halt Enable (Bit 0)
Setting this bit to ‘1’ immediately initiates HALT mode. While in
HALT mode, only the CPU is stopped. The internal clock still runs
and all peripherals still operate, including the USB engines. The
power saving using HALT in most cases is minimal, but in appli-
cations that are very CPU intensive the incremental savings may
provide some benefit.
The HALT state is exited when any enabled interrupt is triggered.
Upon exiting the HALT state, one or two instructions immediately
following the HALT instruction may be executed before the
waking interrupt is serviced (you may want to follow the HALT
instruction with two NOPs).
1: Enable Halt mode
0: No function
Reserved
Write all reserved bits with ’0’.
Host/Device 2 Interrupt Enable (Bit 9)
The Host/Device 2 Interrupt Enable bit enables or disables all of
the following Host/Device 2 hardware interrupts: Host 2 USB
Done, Host 2 USB SOF/EOP, Host 2 Wakeup/Insert/Remove,
Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB,
Device 2 Endpoint n.
1: Enable Host 2 and Device 2 interrupt
0: Disable Host 2 and Device 2 interrupt
Host/Device 1 Interrupt Enable (Bit 8)
The Host/Device 1 Interrupt Enable bit enables or disables all of
the following Host/Device 1 hardware interrupts: Host 1 USB
Done, Host 1 USB SOF/EOP, Host 1 Wakeup/Insert/Remove,
Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB,
Device 1Endpoint n.
1: Enable Host 1 and Device 1 interrupt
0: Disable Host 1 and Device 1 interrupt
Interrupt
Interrupt
Enable
Enable
UART
R/W
R/W
SPI
11
0
3
0
Reserved
Interrupt
Enable
GPIO
R/W
10
0
2
0
-
Host/Device 2
Interrupt
Interrupt
Timer 1
Enable
Enable
R/W
R/W
9
0
1
0
CY7C67300
Host/Device 1
Interrupt
Interrupt
Timer 0
Enable
Enable
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R/W
R/W
8
0
0
0
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