CY7C67300-100AXE Cypress Semiconductor Corp, CY7C67300-100AXE Datasheet - Page 67

• Manufacturer Part Number: CY7C67300-100AXE
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXE

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Control Register [0xC0CA] [R/W]
Table 107. SPI Control Register
Register Description
The SPI Control register controls the SPI port. Fields apply to
both master and slave mode unless otherwise noted.
SCK Strobe (Bit 15)
The SCK Strobe bit starts the SCK strobe at the selected
frequency and polarity (set in the SPI Configuration register), but
not phase. This bit feature can only be enabled when in master
mode and must be during a period of inactivity. This bit is self
clearing.
1: SCK Strobe Enable
0: No Function
FIFO Init (Bit 14)
The FIFO Init bit initializes the FIFO and clears the FIFO Error
Status bit. This bit is self clearing.
1: FIFO Init Enable
0: No Function
Byte Mode (Bit 13)
The Byte Mode bit selects between PIO (byte mode) and DMA
(block mode) operation.
1: Set PIO (byte mode) operation
0: Set DMA (block mode) operation
Full Duplex (Bit 12)
The Full Duplex bit selects between full duplex and half duplex
operation.
1: Enable full duplex. Full duplex is not allowed and does not set
if the 3Wire Enable bit of the SPI Configuration register is set to
‘1’
0: Enable half duplex operation
SS Manual (Bit 11)
The SS Manual bit activates or deactivates SS if the SS Delay
Select field of the SPI Control register is all zeros and is
configured as master interface. This field only applies to master
mode.
1: Activate SS, master drives SS line asserted LOW
0: Deactivate SS, master drives SS line deasserted HIGH
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Transmit
Strobe
Empty
SCK
15
W
R
0
7
1
Receive
FIFO
Full
Init
14
W
R
0
6
0
Mode
Byte
R/W
R/W
13
0
5
0
Transmit Bit Length
Full Duplex
R/W
R/W
12
0
4
0
Read Enable (Bit 10)
The Read Enable bit initiates a read phase for a master mode
transfer or sets the slave to receive (in slave mode).
1: Initiates a read phase for a master transfer or sets a slave to
receive. In master mode this bit is sticky and remains set until the
read transfer begins.
0: Initiates the write phase for slave operation
Transmit Ready (Bit 9)
The Transmit Ready bit is a read only bit that indicates if the
transmit port is ready to empty and ready to be written.
1: Ready for data to be written to the port. The transmit FIFO is
not full.
0: Not ready for data to be written to the port
Receive Data Ready (Bit 8)
The Receive Data Ready bit is a read only bit that indicates if the
receive port has data ready.
1: Receive port has data ready to read
0: Receive port does not have data ready
Transmit Empty (Bit 7)
The Transmit Empty bit is a read only bit that indicates if the
transmit FIFO is empty.
1: Transmit FIFO is empty
0: Transmit FIFO is not empty
Receive Full (Bit 6)
The Receive Full bit is a read only bit that indicates if the receive
FIFO is full.
1: Receive FIFO is full
0: Receive FIFO is not full
Transmit Bit Length (Bits [5:3])
The Transmit Bit Length field controls whether a full byte or
partial byte is to be transmitted. If Transmit Bit Length is ‘000’
then a full byte is transmitted. If Transmit Bit Length is ‘001’ to
‘111’, then the value indicates the number of bits that are be
transmitted.
Manual
R/W
R/W
SS
11
3
0
0
Enable
Read
R/W
R/W
10
2
0
0
Receive Bit Length
Transmit
Ready
R/W
R
1
0
9
0
CY7C67300
Receive
Ready
Page 67 of 99
Data
R/W
R
0
0
8
1
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