MC68EC000EI10 Freescale Semiconductor, MC68EC000EI10 Datasheet - Page 100

• Manufacturer Part Number: MC68EC000EI10
• Description: IC MPU 32BIT 10MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI10

• Processor Type: M680x0 32-Bit
• Speed: 10MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The inclusion of the NAN data type in the IEEE floating-point number system requires each
conditional test to include the NAN condition code bit in its Boolean equation. Because a
comparison of a NAN with any other data type is unordered (i.e., it is impossible to determine
if a NAN is bigger or smaller than an in-range number), the compare instruction sets the
NAN condition code bit when an unordered compare is attempted. All arithmetic instructions
also set the NAN bit if the result of an operation is a NAN. The conditional instructions
interpret the NAN condition code bit equal to one as the unordered condition.
The IEEE 754 standard defines four conditions: equal to (EQ), greater than (GT), less than
(LT), and unordered (UN). In addition, the standard only requires the generation of the
condition codes as a result of a floating-point compare operation. The FPU can test these
conditions at the end of any operation affecting the condition codes. For purposes of the
floating-point conditional branch, set byte on condition, decrement and branch on condition,
and trap on condition instructions, the processor logically combines the four FPCC condition
codes to form 32 conditional tests. There are three main categories of conditional tests:
IEEE nonaware tests, IEEE aware tests, and miscellaneous. The set of IEEE nonaware
tests is best used:
The 32 conditional tests are separated into two groups; 16 that cause an exception if an
unordered condition is present when the conditional test is attempted and 16 that do not
cause an exception. An unordered condition occurs when one or both of the operands in a
floating-point compare operation The inclusion of the unordered condition in floating-point
branches destroys the familiar trichotomy relationship (greater than, equal, less than) that
exists for integers. For example, the opposite of floating-point branch greater than (FBGT)
is not floating-point branch less than or equal (FBLE). Rather, the opposite condition is
floating-point branch not greater than (FBNGT). If the result of the previous instruction was
unordered, FBNGT is true; whereas, both FBGT and FBLE would be false since unordered
fails both of these tests (and sets BSUN). Compiler programmers should be particularly
careful of the lack of trichotomy in the floating-point branches since it is common for
compilers to invert the sense of conditions.
MOTOROLA
• when porting a program from a system that does not support the IEEE standard to a
• when generating high-level language code that does not support IEEE floating-point
conforming system, or
concepts (i.e., the unordered condition).
+ Normalized or Denormalized
– Normalized or Denormalized
+ 0
– 0
+ Infinity
– Infinity
+ NAN
– NAN
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Data Type
Table 3-22. FPCC Encodings
N
0
1
0
1
0
1
0
1
Z
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
I
NAN
Instruction Set Summary
0
0
0
0
0
0
1
1
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