MC68EC000EI10 Freescale Semiconductor, MC68EC000EI10 Datasheet - Page 552

• Manufacturer Part Number: MC68EC000EI10
• Description: IC MPU 32BIT 10MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI10

• Processor Type: M680x0 32-Bit
• Speed: 10MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

CPU32 Instructions
TBLU
TBLUN
7-12
For register interpolate mode, the interpolation occurs using the Dym and Dyn registers
in place of the two table entries. For this mode, only the fractional portion, Dx 7 – 0, is
used in the interpolation and the integer portion, Dx 15 – 8, is ignored. The register
interpolation mode may be used with several table lookup and interpolations to model
multidimensional functions.
Signed table entries range from – 2
range from 0 to 2
respectively. The unsigned and unrounded table results will be zero-extended instead
of sign-extended.
Rounding of the result is optionally selected via the "R" instruction field. If R = 0
(TABLE), the fractional portion is rounded according to the round-to-nearest algorithm.
The rounding procedure can be summarized by the following table:
The adjusted difference is then added to the selected table entry. The rounded result
is returned in the destination data register, Dx. Only the portion of the register
corresponding to the selected size is affected.
If R = 1 (TBLUN), the result is returned in register Dx without rounding. If the size is
byte, the integer portion of the result is returned in Dx 15 – 8; the integer portion of a
word result is stored in Dx 23 – 8; the least significant 24 bits of a long result are stored
in Dx 31 – 8. Byte and word results are sign-extended to fill the entire 32-bit register.
WORD
LONG
BYTE
Table Lookup and Interpolation (Unsigned)
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
31
UNAFFECTED
UNAFFECTED
n – 1
RESULT
Adjusted Difference
where n is 8, 16, or 32 for byte, word, and long-word tables,
24
Fraction
< 1/2
1/2
23
UNAFFECTED
UNAFFECTED
RESULT
n – 1
(CPU32)
to 2
16
n – 1
Rounding
Adjustme
+ 1
+ 0
nt
– 1; whereas, unsigned table entries
15
UNAFFECTED
RESULT
RESULT
8
7
RESULT
RESULT
RESULT
TBLUN
TBLU
MOTOROLA
0