MC68EC000EI10 Freescale Semiconductor, MC68EC000EI10 Datasheet - Page 487

• Manufacturer Part Number: MC68EC000EI10
• Description: IC MPU 32BIT 10MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI10

• Processor Type: M680x0 32-Bit
• Speed: 10MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PFLUSH
Instruction Format:
Instruction Fields:
MOTOROLA
15
1
0
Effective Address field—Specifies a control alterable address. The address translation
14
cache entry for this address is invalidated. Valid addressing modes are in the
following table:
1
0
13
The address field must provide the memory management unit
with the effective address to be flushed from the address
translation cache, not the effective address describing where the
PFLUSH operand is located. For example, to flush the address
translation cache entry corresponding to a logical address that
is temporarily stored on top of the system stack, the instruction
PFLUSH [(SP)] must be used since PFLUSH (SP) would
invalidate the address translation cache entry mapping the
system stack (i.e., the effective address passed to the memory
management unit is the effective address of the system stack,
not the effective address formed by the operand located on the
top of the stack).
1
1
Addressing Mode
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
12
1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
(bd,An,Xn)
(d
(d
—(An)
8
(An) +
,An,Xn)
(An)
16
MODE
Dn
An
,An)
11
0
Flush Entry in the ATC
10
0
Mode
010
101
110
110
110
110
—
—
—
—
9
0
0
(MC68030 only)
reg. number:An
reg. number:An
reg. number:An
reg. number:An
reg. number:An
reg. number:An
8
0
0
NOTE
Register
—
—
—
—
7
0
MASK
6
0
Addressing Mode
Supervisor (Privileged) Instructions
5
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
(d
(bd,PC,Xn)
# < data >
(d
(xxx).W
(xxx).L
8
MODE
,PC,Xn)
16
4
,PC)
EFFECTIVE ADDRESS
3
PFLUSH
FC
Mode
2
111
111
—
—
—
—
—
—
REGISTER
1
Register
000
001
—
—
—
—
—
—
6-33
0