MC68EC000EI10 Freescale Semiconductor, MC68EC000EI10 Datasheet - Page 95

• Manufacturer Part Number: MC68EC000EI10
• Description: IC MPU 32BIT 10MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI10

• Processor Type: M680x0 32-Bit
• Speed: 10MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Instruction Set Summary
3.5.1 Intermediate Result
All FPU calculations use an intermediate result. When the FPU performs any operation, the
calculation is carried out using extended-precision inputs, and the intermediate result is
calculated as if to produce infinite precision. After the calculation is complete, the
intermediate result is rounded to the selected precision and stored in the destination.
Figure 3-1 illustrates the intermediate result format. The intermediate result’s exponent for
some dyadic operations (i.e., multiply and divide) can easily overflow or underflow the 15-
bit exponent of the designation floating-point register. To simplify the overflow and underflow
detection, intermediate results in the FPU maintain a 16-bit (17 bits for the MC68881 and
MC68882), twos complement, integer exponent. Detection of an overflow or underflow
intermediate result always converts the 16-bit exponent into a 15-bit biased exponent before
being stored in a floating-point data register. The FPU internally maintains the 67-bit
mantissa for rounding purposes. The mantissa is always rounded to 64 bits (or less,
depending on the selected rounding precision) before it is stored in a floating-point data
register.
If the destination is a floating-point data register, the result is in the extended-precision
format and is rounded to the precision specified by the FPSR PREC bits before being stored.
All mantissa bits beyond the selected precision are zero. If the single- or double-precision
mode is selected, the exponent value is in the correct range even if it is stored in extended-
precision format. If the destination is a memory location, the FPSR PREC bits are ignored.
In this case, a number in the extended-precision format is taken from the source floating-
point data register, rounded to the destination format precision, and then written to memory.
Depending on the selected rounding mode or destination data format in effect, the location
of the least significant bit of the mantissa and the locations of the guard, round, and sticky
bits in the 67-bit intermediate result mantissa varies. The guard and round bits are always
calculated exactly. The sticky bit is used to create the illusion of an infinitely wide
intermediate result. As the arrow illustrates in Figure 3-1, the sticky bit is the logical OR of
all the bits in the infinitely precise result to the right of the round bit. During the calculation
stage of an arithmetic operation, any non-zero bits generated that are to the right of the
round bit set the sticky bit to one. Because of the sticky bit, the rounded intermediate result
for all required IEEE arithmetic operations in the RN mode is in error by no more than one
half unit in the last place.
3-24
16-BIT EXPONENT
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Figure 3-1. Intermediate Result Format
INTEGER BIT
OVERFLOW BIT
.
63-BIT MANTISSA
LSB OF FRACTION
ROUND BIT
GUARD BIT
STICKY BIT
MOTOROLA