MC68EC000EI10 Freescale Semiconductor, MC68EC000EI10 Datasheet - Page 37

• Manufacturer Part Number: MC68EC000EI10
• Description: IC MPU 32BIT 10MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI10

• Processor Type: M680x0 32-Bit
• Speed: 10MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Introduction
Because address registers and stack pointers are 32 bits wide, address registers cannot be
used for byte-size operands. When an address register is a source operand, either the low-
order word or the entire long-word operand is used, depending upon the operation size.
When an address register is the destination operand, the entire register becomes affected,
despite the operation size. If the source operand is a word size, it is sign-extended to 32 bits
and then used in the operation to an address register destination. Address registers are
primarily for addresses and address computation support. The instruction set includes
instructions that add to, compare, and move the contents of address registers. Figure 1-19
illustrates the organization of addresses in address registers.
1-26
31
31
* IF WIDTH + OFFSET > 32, BIT FIELD WRAPS AROUND WITHIN THE REGISTER.
MSB
MSB
MSB
31
31
31
31
63
31
31
31
31
Figure 1-19. Organization of Integer Data Formats in Address Registers
Figure 1-18. Organization of Integer Data Formats in Data Registers
30
OFFSET
SIGN-EXTENDED
NOT USED
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8
8
NOT USED
7
7
MOST SIGNIFICANT DIGIT
ANY DY
LONG WORD
UNDEFINED
FULL 32-BIT ADDRESS OPERAND
WIDTH*
ANY DX
MSB
15
16 15
.
4
4
LOW-ORDER WORD
3
3
LEAST SIGNIFICANT DIGIT
LEAST SIGNIFICANT DIGIT
MSB
7
16-BIT ADDRESS OPERAND
1
LSB
32
LSB
LSB
LSB
LSB
0
0
0
0
0
0
0
0
BIT (0 MODULO (OFFSET)
< 31,OFFSET OF 0 = MSB)
BYTE
16-BIT WORD
LONG WORD
BIT FIELD (0 < OFFSET < 32,
0 < WIDTH 32)
UNPACKED BCD
PACKED BCD
QUAD WORD
< _
< _
MOTOROLA
0
0