MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 16

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RESET Initialization
4.5
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,
see the specific section of this document.
5
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8544E.
component(s).
Table 9
6
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8544E. Note that DDR SDRAM is GV
16
Required assertion time of HREST
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before HRESET
negation
Input setup time for POR configs (other than PLL config) with
respect to negation of HRESET
Input hold time for all POR configs (including PLL config) with
respect to negation of HRESET
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of HRESET
Note:
1. SYSCLK is the primary clock input for the MPC8544E.
Core and platform PLL lock times
Local bus PLL
PCI bus lock time
RESET Initialization
DDR and DDR2 SDRAM
provides the PLL lock times.
Other Input Clocks
Table 8
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter/Condition
Parameter/Condition
provides the RESET initialization AC timing specifications for the DDR SDRAM
Table 8. RESET Initialization Timing Specifications
Table 9. PLL Lock Times
DD
(typ) = 2.5 V and DDR2 SDRAM is GV
Min
100
100
—
3
4
2
Min
—
—
—
Max
—
—
—
—
—
5
1
Max
100
50
50
Freescale Semiconductor
SYSCLKs
SYSCLKs
SYSCLKs
SYSCLKs
Unit
DD
μs
μs
Unit
μs
μs
(typ) = 1.8 V.
μs
Notes
Notes
—
—
—
—
—
1
1
1
1