MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 33

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.5.2.2
Table 31
Figure 14
Figure 15
8.6
This section describes the MII transmit and receive AC timing specifications.
Freescale Semiconductor
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
RX_CLK clock period
RX_CLK duty cycle
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RX_CLK to RXD[7:0], RX_DV, RX_ER hold time
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
1. The symbols used for timing specifications follow the pattern of t
inputs and t
timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
going to the high state (H) or setup time. Also, t
input signals (D) went invalid (X) relative to the t
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
is used with the appropriate letter: R (rise) or F (fall).
provides the GMII receive AC timing specifications.
MII AC Timing Specifications
provides the AC test load for eTSEC.
shows the GMII receive AC timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
GMII Receive AC Timing Specifications
Parameter/Condition
RXD[7:0]
RX_CLK
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
RX_DV
RX_ER
Output
GRX
Table 31. GMII Receive AC Timing Specifications
Figure 15. GMII Receive AC Timing Diagram
represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention
t
t
GRXH
GRDVKH
Figure 14. eTSEC AC Test Load
t
GRX
Z
GRDXKL
GRX
0
= 50 Ω
clock reference (K) going to the low (L) state or hold time. Note that, in
symbolizes GMII receive timing (GR) with respect to the time data
t
GRXH
Symbol
t
t
GRDXKH
GRDVKH
t
t
t
GRXR
GRXF
GRX
t
/t
GRXF
GRX
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
1
t
GRDXKH
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Min
R
2.0
0.5
—
—
—
35
L
t
GRXR
= 50 Ω
Typ
8.0
—
—
—
—
—
LV
GRDVKH
DD
/2
Max
1.0
1.0
65
—
—
—
symbolizes GMII receive
RX
clock reference (K)
Unit
ns
ns
ns
ns
ns
%
Notes
—
—
—
—
—
—
for
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