MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 104

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Operands of locked instructions (CAS and TAS) and operand references while the lock bit
in the bus control register is set which miss in the data cache do not allocate for reads or
writes regardless of the caching mode, and therefore will bypass the cache. Locked instruc-
tions that hit in the data cache invalidate a matching valid entry or will push and invalidate a
matching dirty entry. The locked operand access will then bypass the cache.
5.2 CACHE CONTROL REGISTER
The cache control register (CACR) is a 32-bit register which contains control information for
the instruction and data caches. A MOVEC sets all of the bits in the CACR. A hardware reset
clears the CACR, disabling both caches; however, reset does not affect the tags, state infor-
mation, and data within the caches. The CACR is illustrated in Figure 5-5.
EDC—Enable Data Cache
NAD—No Allocate Mode (Data Cache)
ESB—Enable Store Buffer
DPI—Disable CPUSH Invalidation
FOC—1/2 Cache Operation Mode Enable (Data Cache)
MOTOROLA
EDC
31
Locked write accesses and accesses to cache-inhibited precise pages always bypass the
store buffer.
0 = Data cache is disabled.
1 = Data cache is enabled.
0 = Read and write misses will allocate in the data cache.
1 = Read and write misses will not allocate in the data cache.
0 = All writes to writethrough or cache-inhibited imprecise pages will bypass the store
1 = The four entry first-in-first-out (FIFO) store buffer to the MC68060 is enabled. This
0 = Each cache line is invalidated as it is pushed. Affects only the data cache.
1 = CPUSHed lines remain valid in the cache.
0 = The data cache operates in normal, full-cache mode.
1 = The data cache operates in 1/2-cache mode.
NAD
30
buffer and generate bus cycles directly.
buffer is used to defer pending writes to writethrough or cache-inhibited imprecise
pages to maximize performance.
ESB
29
DPI
28
FOC
27
26
0 0 0
Figure 5-5. Cache Control Register
24
EBC
23
M68060 USER’S MANUAL
CABC
22
CUBC
21
20
0 0 0 0 0
16
EIC
15
NAI
14
FIC
13
12
0 0 0 0 0 0 0 0 0 0 0 0 0
Caches
5-5
0