MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 150

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Floating-Point Unit
The user UNFL handler must execute an FSAVE instruction as the first floating-point instruc-
tion to prevent further exceptions from reporting. The address of the instruction that causes
the overflow is available to the user UNFL handler in the FPIAR. By examining the instruc-
tion, the user UNFL handler can determine the arithmetic operation type and destination
location. The exception operand is stored in the floating-point state frame (generated by the
FSAVE). When an underflow occurs, the exception operand is defined differently for various
destination types:
In addition to normal underflow, the exponential instructions (e
FSCALE) may generate results that grossly underflow the 16-bit exponent of the internal in-
termediate format. When such an underflow occurs (called a catastrophic underflow), the
exception operand exponent value is set to $0000. This value is easily distinguished from
the exception operand exponent values produced by normal underflow processing.
If an INEX2 or INEX1 exceptional condition exists and the user INEX exception is enabled,
it is the responsibility of the user UNFL exception handler to handle this lower priority inexact
exception. The user UNFL exception handler may discard the floating-point state frame
once the handler has completed. The RTE instruction must be executed to return to normal
instruction flow.
6.6.6 Divide-by-Zero
This exception happens when a zero divisor occurs for a divide instruction or when a tran-
scendental function is asymptotic with infinity as the asymptote. Table 6-15 lists the instruc-
tions that can cause the divide-by-zero exception. Note that only the FDIV and FSGLDIV
instructions are native to the MC68060. The other conditions occur only if the M68060SP is
used. When a divide-by-zero is detected, the DZ bit is set in the FPSR EXC byte. The divide-
by-zero exception only has maskable exceptional conditions. An exception is taken only if
the DZ bit is set in FPSR EXC byte and the corresponding bit in the FPCR exception enable
byte is set.
6-32
1. FMOVE OUT (memory or integer data register destination)—the value in the excep-
2. Floating-point data register destination—the value in the exception operand is the in-
tion operand is the intermediate result mantissa rounded to the destination precision,
with a 15-bit exponent biased as a normal extended-precision number. In the case of
a memory destination, the evaluated effective address of the operand is available in
the stack frame format $3. This allows the user UNFL handler to overwrite the default
result, if necessary, without recalculating the effective address.
termediate result mantissa rounded to extended precision, with an exponent bias of
$3FFF + $6000 rather than $3FFF. The additional bias of +$6000 is used so that it is
possible to represent the smaller exponent in a 15-bit format.
M68060 USER’S MANUAL
x
, 10
x
, 2
x
, SINH, COSH, and
MOTOROLA