MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 105

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Caches
Bits 26–24—Reserved.
EBC—Enable Branch Cache
CABC—Clear All Entries in the Branch Cache
CUBC—Clear All User Entries in the Branch Cache
Bits 20–16—Reserved.
EIC—Enable Instruction Cache
NAI—No Allocate Mode (Instruction Cache)
FIC—1/2 Cache Operation Mode Enable (Instruction Cache)
Bits 13–0—Reserved.
5.3 CACHE MANAGEMENT
The caches are individually enabled and configured by using the MOVEC instruction to
access the CACR. A hardware reset clears the CACR, disabling both caches and removing
all configuration information; however, reset does not affect the tags, state information, and
data within the caches. The CINV instruction must clear the caches before enabling them.
The MC68060 cannot cache page descriptors.
System hardware can assert the cache disable (CDIS) signal to dynamically disable the both
the instruction and data caches, regardless of the state of the enable bits in the CACR. The
caches are disabled immediately after the current access completes. If CDIS is asserted
during the access for the first half of a misaligned operand spanning two cache lines, the
5-6
This bit is always read as zero.
This bit is always read as zero.
0 = The branch cache is disabled and branch cache information is not used in the
1 = The on-chip branch cache is enabled. Branches are cached. A predicted branch
0 = No operation is done on the branch cache.
1 = The entire content of the MC68060 branch cache is invalidated.
0 = No operation is performed on the branch cache.
1 = All user-mode entries in the MC68060 branch cache are invailidated; supervisor-
0 = Instruction cache is disabled.
1 = Instruction cache is enabled.
0 = Accesses that miss in the instruction cache will allocate.
1 = The instruction cache will continue to supply instructions to the processor, but an
0 = The instruction cache operates in normal, full-cache mode.
1 = The instruction cache operates in 1/2-cache mode.
branch prediction strategy.
executes more quickly, and often can be folded onto another instruction.
mode branch cache entries remain valid.
access that misses will not allocate.
M68060 USER’S MANUAL
MOTOROLA