MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 231

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Bus Operation
The ignore state settings can be used to make the system design of the acknowledge ter-
mination logic simpler than in existing MC68040 systems that required these signals to be
valid (either asserted or negated) about every rising BCLK edge. Thus, using the acknowl-
edge termination ignore state capability allows the use of slower ASICs and PALs to be used
for generating the acknowledge termination signals without the requirement that these sig-
nals be at a valid logic level about every rising BCLK edge.
7.14.2 Acknowledge Termination Protocol
The MC68060 provides system designers a choice of using either the MC68040 acknowl-
edge termination protocol or the native-MC68060 acknowledge termination protocol. The
native-MC68060 acknowledge termination protocol is chosen if IPL1 is asserted during
reset.
The MC68040 acknowledge termination protocol is provided for MC68040 compatibility. In
this protocol, a retry is indicated by having both TA and TEA asserted simultaneously. In this
mode, the TRA signal must be pulled up at all times. Refer to Table 7-4 and Table 7-5 for
details on acknowledge termination signal encoding.
The native-MC68060 acknowledge termination protocol is provided to aid in high-frequency
designs. The signal TRA is used to indicate a retry operation, as opposed to using a combi-
nation of TA and TEA to indicate a retry. Refer to Table 7-4 and Table 7-5 for details on the
native-MC68060 acknowledge termination signal encoding.
7.14.3 Extra Data Write Hold Time Mode
In this mode, the MC68060 holds the contents of the data bus valid during a write bus cycle
for an extra BCLK period after a valid TA is sampled. This mode is enabled if IPL2 is
asserted during reset. When this mode is enabled, a zero wait state burst bus cycle is not
possible and systems must be designed to insert wait states on burst accesses. Figure 7-
52 shows an example of a line transfer cycle with this mode enabled. Read cycles are unaf-
fected by this mode.
7-76
M68060 USER’S MANUAL
MOTOROLA