MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 68

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Integer Unit
The supervisor programming model consists of the registers available to the user as well as
the following control registers:
The following paragraphs describe the supervisor programming model registers. Additional
information on the SSP, SR, and VBR registers can be found in Section 8 Exception Pro-
cessing.
3.2.2.1 SUPERVISOR STACK POINTER. When the MC68060 is operating at the supervi-
sor level, instructions that use the system stack implicitly, or access address register A7
explicitly, use the SSP. The SSP is a general-purpose register and can be used as a soft-
ware stack pointer, index register, or base address register. The SSP can be used for word
and long-word operations. The initial value of the SSP is loaded from the reset exception
vector, address offset 0.
3.2.2.2 STATUS REGISTER. The SR (see Figure 3-4) stores the processor status and
includes the CCR, the interrupt priority mask, and other control bits. In the supervisor mode,
software can access the entire SR. The control bits indicate the following states for the pro-
cessor: trace mode (T-bit), supervisor or user mode (S-bit), and master or interrupt state (M).
3.2.2.3 VECTOR BASE REGISTER. The VBR contains the base address of the exception
vector table in memory. The displacement of an exception vector is added to the value in
this register to access the vector table. Refer to Section 8 Exception Processing for infor-
mation on exception vectors.
3-4
• 32-Bit Supervisor Stack Pointer (SSP, A7)
• 16-Bit Status Register (SR)
• 32-Bit Vector Base Register (VBR)
• Two 32-Bit Alternate Function Code Registers: Source Function Code (SFC) and Des-
• 32-Bit Processor Configuration Register (PCR)
TRACE ENABLE
SUPERVISOR/USER STATE
MASTER/INTERRUPT STATE
tination Function Code (DFC)
15
T
14
0
13
S
SYSTEM BYTE
12
M
Figure 3-4. Status Register
11
0
M68060 USER’S MANUAL
10
I2
PRIORITY MASK
INTERRUPT
9
I1
I0
8
7
0
6
0
(CONDITION CODE REGISTER)
5
0
USER BYTE
4
X
3
N
2
Z
1
V
0
C
CARRY
OVERFLOW
MOTOROLA
ZERO
NEGATIVE
EXTEND