MC68306FC16B Freescale Semiconductor, MC68306FC16B Datasheet - Page 170

• Manufacturer Part Number: MC68306FC16B
• Description: IC MPU INTEGRATED 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68306FC16B

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

8.7 AC ELECTRICAL SPECIFICATIONS—READ AND WRITE
CYCLES
NOTES:
8-6
31 2,5
Num
20A
21A
29A
47 5
48 3
56 4
21
22
25
26
27
28
23
29
30
32
53
55
1.
2.
3.
4.
5.
6.
7.
8.
9.
2
2
2
2
5
2
6
2
For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the
maximum columns.
Actual value depends on clock period.
If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR
is an asynchronous input using the asynchronous input setup time (#47).
For power-up, the MC68306 must be held in the reset state for 100 ms to allow stabilization of on-chip
circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the
controller.
If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data
setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time
(#27) for the following clock cycle.
When AS and R/W are equally loaded ( 20%), subtract 5 ns from the values given in these columns.
The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before
asserting BGACK.
The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be
reasserted.
AS is always asserted, regardless of whether it is mapped to internal or external resources. If the designer
wishes to decode more chip selects than are provided, use one of CS0–7 as the enable for the external decode.
AS Asserted to R/W Low (Write)
Address Valid to R/W Low (Write)
FC Valid to R/W Low (Write)
R/ W Low to LDS, UDS Asserted (Write)
CLKOUT Low to Data-Out Valid (Write)
AS, LDS, UDS Negated to Data-Out Invalid (Write)
Data-Out Valid to LDS, UDS Asserted (Write)
Data-In Valid to CLKOUT Low (Setup Time on Read)
AS, LDS, UDS Negated to DTACK Negated (Asynchronous
Hold)
AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read)
AS, LDS, UDS Negated to Data-In High Impedance
AS, LDS, UDS Negated to BERR Negated
DTACK Asserted to Data-In Valid (Setup Time)
HALT and RESET Input Transition Time
Asynchronous Input Setup Time
BERR Asserted to DTACK Asserted
Data-Out Hold from CLKOUT High
R/ W Asserted to Data Bus Impedance Change
HALT/RESET Pulse Width
(Continued)
Freescale Semiconductor, Inc.
Characteristic
For More Information On This Product,
MC68306 USER'S MANUAL
Go to: www.freescale.com
Min
16.67 MHz
30
30
15
15
10
10
—
—
—
—
—
0
5
0
0
0
5
0
0
Max
110
150
10
30
90
50
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
Clks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MOTOROLA