MC68306FC16B Freescale Semiconductor, MC68306FC16B Datasheet - Page 176

• Manufacturer Part Number: MC68306FC16B
• Description: IC MPU INTEGRATED 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68306FC16B

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

8.10 BUS OPERATION—DRAM ACCESSES AC TIMING
SPECIFICATIONS
Num.
8-12
71A
89A
100
101
102
103
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
NOTES:
1. On write portion of TAS, CAS assertion is gated by UDS/LDS (not CLKOUT as in all other operation).
2. Page mode is used on Read-Modify-Write (TAS instruction) cycles only.
CLKOUT High to RAS≈ Asserted (0 Wait State Operation)
AS Asserted to RAS≈ Asserted (0 Wait State Operation)
CLKOUT Low to RAS≈ Asserted (1 Wait State Operation)
CLKOUT Low to Row Address Valid
Row Address Valid to RAS≈ Asserted
RAS≈ Asserted to Row Address Invalid
CLKOUT High to Row Address Invalid (0 Wait State Operation)
CLKOUT Low to Row Address Invalid (1 Wait State Operation)
RAS≈ Width Asserted (Non-Page Mode)
RAS≈ Width Asserted (Page Mode)
RAS≈ Width Negated (Back to Back Cycles)
RAS≈ Asserted to CAS≈ Asserted
CLKOUT High to Column Address Valid (0 Wait State Operation)
CLKOUT Low to Column Address Valid (1 Wait State Operation)
CLKOUT Low to CAS≈ Asserted (0 Wait State Operation)
CLKOUT High to CAS≈ Asserted (1 Wait State Operation)
Column Address Valid to CAS≈ Asserted
CAS≈ Asserted to Column Address Invalid
CAS≈ Width Asserted
CLKOUT Low to RAS≈ /CAS≈ Negated
AS Negated to RAS≈ /CAS≈ Negated
CAS≈ Width Negated (Back to Back Cycles)
CAS≈ Width Negated (Page Mode
UDS/LDS Asserted to CAS≈ Asserted
DRAMW Low to CAS≈ Asserted (Write)
Data Out Valid to CAS≈ Asserted (Write)
CLKOUT Low to CAS≈ Asserted (Refresh Cycle)
CLKOUT High to CAS≈ Negated (Refresh Cycle)
CAS≈ Width Asserted (Refresh Cycle)
CAS≈ Asserted to RAS≈ Asserted (Refresh Cycle)
CLKOUT High to RAS≈ Asserted (Refresh Cycle)
CLKOUT Low to RAS≈ Negated (Refresh Cycle)
RAS≈ Width Asserted (Refresh Cycle)
DRAMW High to RAS≈ Asserted (Refresh Cycle)
DRAMW High Hold After RAS≈ Asserted (Refresh Cycle)
(The electrical specifications in this document are preliminary. See Figures 8-8–8-11)
Freescale Semiconductor, Inc.
Characteristic
For More Information On This Product,
2
)
MC68306 USER'S MANUAL
1
Go to: www.freescale.com
(Page Mode
2
)
Min
120
480
150
240
15
20
60
45
20
75
60
30
15
80
20
80
20
20
0
0
–
0
0
–
0
–
0
–
0
0
0
0
0
0
0
0-Wait
Max
180
540
300
120
120
30
10
30
30
20
90
30
10
10
20
20
60
30
25
60
16.67 MHz
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
150
100
180
240
510
140
140
30
40
90
60
20
90
60
45
20
20
20
–
–
0
0
–
0
–
0
–
0
0
0
0
0
0
0
0
1-Wait
Max
210
300
570
120
180
180
25
30
30
20
30
10
10
20
60
30
25
60
MOTOROLA
20
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns