MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 494

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
HDLC, particularly the framing structure of HDLC: namely, SDLC, SS#7, AppleTalk, LAPB,
and LAPD. The framing structure of HDLC is shown in Figure 7-50.
HDLC uses a zero insertion/deletion process (commonly known as bit-stuffing) to ensure
that the bit pattern of the delimiter flag does not occur in the fields between flags. The HDLC
frame is synchronous and therefore relies on the physical layer to provide a method of clock-
ing and synchronizing the transmitter/receiver.
Since the layer 2 frame can be transmitted over a point-to-point link, a broadcast network,
or packet and circuit switched systems, an address field is needed to carry the frame's des-
tination address. The length of this field is commonly 0, 8, or 16 bits, depending on the data
link layer protocol. For instance, SDLC and LAPB use an 8-bit address. SS#7 has no
address field at all because it is always used in point-to-point signaling links. LAPD further
divides its 16-bit address into different fields to specify various access points within one
piece of equipment. It also defines a broadcast address. Some HDLC-type protocols also
allow for extended addressing beyond 16 bits.
The 8 or 16-bit control field provides a flow control number and defines the frame type (con-
trol or data). The exact use and structure of this field depends upon the protocol using the
frame.
Data is transmitted in the data field, which can vary in length depending upon the protocol
using the frame. Layer 3 frames are carried in this data field.
Error control is implemented by appending a CRC (CRC) to the frame, which in most proto-
cols is 16-bits long but may be as long as 32-bits.
In HDLC, the LSB of each octet is transmitted first, and the MSB of the CRC is transmitted
first.
When the MODE bits of the GSMR select the HDLC mode, then that SCC functions as an
HDLC controller. When an SCC in HDLC mode is used with a nonmultiplexed modem inter-
face, then the SCC outputs are connected directly to the external pins. Modem signals may
be supported through the port C pins. The receive and transmit clocks can be supplied either
from the bank of baud rate generators, by the DPLL, or externally. The HDLC controller may
also be connected to one of the two TDM channels of the serial interface and used with the
TSA.
The HDLC controller consists of separate transmit and receive sections whose operations
are asynchronous with the CPU32+ core and may be either synchronous or asynchronous
with respect to the other SCCs. The user can allocate up to 196 BDs for receive and transmit
tasks so that many frames may be transmitted or received without host intervention.
7.10.17.1 HDLC CONTROLLER KEY FEATURES. The HDLC contains the following key
features:
7-170
• Flexible Data Buffers with Multiple Buffers per Frame
• Separate Interrupts for Frames and Buffers (Receive and Transmit)
• Received Frames Threshold To Reduce Interrupt Overhead
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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