MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 523

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

7.10.19.4.1 GSMR Programming. The GSMR programming sequence is as follows:
MOTOROLA
1. The MODE bits should be set to AppleTalk.
2. The ENT and ENR bits should be set.
3. The DIG bits should be set for normal operation, with the CD and CTS pins
4. The RDCR and TDCR bits should usually be set to 16x clock.
5. The TENC and RENC bits should be set for FM0.
6. The Tend bit should be zero.
7. The TPP bits should be 11.
8. The TPL bits should be set to 000 to transmit the next frame with no
9. The TINV and RINV bits should be zero.
10. The TSNC bits should be set to 1.5 bit times 10.
11. The EDGE bits should be zero.
12. RTSM should be zero.
13. All other bits should be set to zero or to their default condition.
RTS
TXD
grounded or with the CD and CTS pins configured for parallel I/O, which causes
CD and CTS to be internally asserted to the SCC.
synchronization sequence and to 001 to transmit the next frame with
the LocalTalk synchronization sequence. For example, data frames do
not require a preceding synchronization sequence. These bits may be
modified on the fly if the AppleTalk protocol is selected.
SYNC
6-BIT
SEQ
STANDARD HDLC FRAME HANDLING
FLAGS
HDLC
TWO
Figure 7-62. Connecting the QUICC to LocalTalk
ADDR.
DEST.
Freescale Semiconductor, Inc.
QUICC
SCC
For More Information On This Product,
SOURCE
ADDR.
RXD
TXD
RTS
CONTROL
MC68360 USER’S MANUAL
Go to: www.freescale.com
BYTE
STORED IN TRANSMIT BUFFER
STORED IN RECEIVE BUFFER
TX ENABLE
Tx DATA
Rx DATA
RS-422
DATA
Serial Communication Controllers (SCCs)
MINI-DIN 8
CRC-16
CLOSING
FLAG
16 ONES
(ABORT)
7-199