MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 535

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

RVD—Reverse Data
DRT—Disable Receiver While Transmitting
Bits 5–4—Reserved
RPM—Receiver Parity Mode
TPM—Transmitter Parity Mode
7.10.20.12 BISYNC RECEIVE BUFFER DESCRIPTOR (RX BD). The CP reports informa-
tion about the received data for each buffer using BDs. The CP closes the current buffer,
MOTOROLA
The RPM bits select the type of parity check to be performed by the receiver. The RPM
bits can be modified on the fly. The RPM bits are ignored unless the CRC bits are selected
to be LRC.
When odd parity is selected, the transmitter will count the number of ones in the data
word. If the total number of ones is not an odd number, the parity bit is set to one and thus
produces an odd number. If the receiver counts an even number of ones, an error in trans-
mission has occurred. In the same manner, for even parity, an even number must result
from the calculation performed at both ends of the line. In high/low parity, if the parity bit
is not high/low, a parity error is reported. The receive parity errors cannot be disabled, but
can be ignored if desired.
The TPM bits select the type of parity to be performed by the transmitter. The TPM bits
can be modified on the fly. The TPM bits are ignored unless the CRC bits are selected to
be LRC.
0 = Normal operation.
1 = Any portion of this SCC that is defined to operate in BISYNC mode (either the re-
0 = Normal operation.
1 = While data is being transmitted by the SCC, the receiver is disabled, being gated
00 = Odd Parity
01 = Low Parity (always check for a zero in the parity bit position)
10 = Even Parity
11 = High Parity (always check for a one in the parity bit position)
00 = Odd Parity
01 = Force Low Parity (always send a zero in the parity bit position)
10 = Even Parity
11 = Force High Parity (always send a one in the parity bit position)
ceiver or transmitter or both) will operate by reversing the character bit order, trans-
mitting the MSB first.
by the internal RTS signal. This is useful if the BISYNC channel is being configured
onto a multidrop line, and the user does not wish to receive his own transmission.
Note that although BISYNC is usually implemented as a half-duplex protocol, the
receiver is not actually disabled during transmission. Thus, for typical BISYNC op-
eration, DRT should not be set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)
7-211