KSZ8893MBL Micrel Inc, KSZ8893MBL Datasheet - Page 15

• Manufacturer Part Number: KSZ8893MBL
• Description: IC MANAGED SW 10/100 100-LFBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8893MBL

• Controller Type: Ethernet Switch Controller
• Interface: MII, RMII, SNI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3090

December 2007
Note:
1. P = Power supply.
Pin Number
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Gnd = Ground.
I = Input.
O = Output.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
I/O = Bi-directional.
Pin Name
LEDSEL0
SMTXEN
SMTXD3
SMTXD2
SMTXD1
SMTXD0
SMTXER
SMTXC /
REFCLK
DGND
VDDIO
SMRXC
SMRXDV
SMRXD3
SMRXD2
SMRXD1
SMRXD0
SCOL
SCRS
Type
I
I
I
I
I
I
I
I/O
Gnd
P
I/O
O
Ipd/O
Ipd/O
Ipd/O
I/O
I/O
I/O
(1)
15
Description
LED display mode select
See description in pins 1 and 4.
Switch MII transmit enable
Switch MII transmit data bit 3
Switch MII transmit data bit 2
Switch MII transmit data bit 1
Switch MII transmit data bit 0
Switch MII transmit error
Switch MII transmit clock (MII and SNI modes only)
Reference Clock (RMII mode only)
Note: In RMII mode, pin X1 is pulled up to VDDIO supply with
a 10K resistor and pin X2 is a no connect.
Digital ground
3.3V digital V
Switch MII receive clock.
Switch MII receive data valid
Switch MII receive data bit 3
Strap option: switch MII full-duplex flow control
Switch MII receive data bit 2
Strap option: switch MII is in
Switch MII receive data bit 1
Strap option: Switch MII is in
Switch MII receive data bit 0
Strap option: switch will accept packet size up to
Switch MII collision detect
Switch MII carrier sense
Output in PHY MII mode and SNI mode
Input in MAC MII mode
Input for 50MHz +/- 50ppm system clock
Output in PHY MII mode
Input in MAC MII mode
PD (default) = disable
PU = enable
PD (default) = full-duplex mode
PU = half-duplex mode
PD (default) = 100Mbps mode
PU = 10Mbps mode
PD = 1536 bytes (inclusive)
PU = 1522 bytes (tagged), 1518 bytes (untagged)
DD
M9999-121007-1.5