DP83257VF National Semiconductor, DP83257VF Datasheet - Page 102

• Manufacturer Part Number: DP83257VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83257VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83257VF

PMID
PMID
PMRD
PMRD
SD
SD
TEL
TXE
Symbol
6 0 Signal Descriptions
6 3 DP83257VF SIGNAL DESCRIPTIONS
The pin descriptions for the DP83257VF are divided into five functional interfaces PMD Interface PHY Port Interface Control
Bus Interface Clock Interface and Miscellaneous Interface
For a Pinout Summary List refer to Table 8-3 and Figure 8-3 DP83257VF 160-Pin JEDEC Metric PQFP Pinout
PMD INTERFACE
The PMD Interface consists of I O signals used to connect the PLAYER
sublayer
The DP83257 PLAYER
The Primary PMD Interface should be used for all PMD implementations that do not require an external scrambler descrambler
function clock recovery function or clock generation function such as a Fiber Optic or Shielded Twisted Pair (SDDI) PMD The
second Alternate PMD Interface can be used to support Unshielded Twisted Pair (UTP) PMDs that require external scrambling
with no external clock recovery or clock generation functions required
Section 3 8 describes how the PLAYER
Note that when the Alternate PMD Interface is not being used the pins that make up the interface must be connected in the
specific way described in the following Alternate PMD Interface table
Primary PMD Interface
a
b
a
b
a
b
Pin
62
61
54
53
60
59
74
73
I O
O
O
I
I
I
a
PMD Indicate Data Differential 100k ECL 125 Mbps serial data input signals from the PMD Receiver
into the Clock Recovery Module (CRM) of the PLAYER
PMD Request Data Differential 100k ECL 125 Mbps serial data output signals to the PMD transmitter
Signal Detect Differential 100k ECL input signals from the PMD receiver indicating that a signal is being
received by the PMD receiver
PMD Transmitter Enable Level A TTL input signal to select the PMD transmitter Enable (TXE) signal
level
PMD Transmitter Enable A TTL output signal to enable disable the PMD transmitter The output level
of the TXE pin is determined by three parameters the Transmit Enable (TE) bit in the Mode Register the
TM2–TM0 bits in the Current Transmit State Register and the input to the TEL pin The following rules
summarize the output of the TXE pin
1 If TE
2 If TE
3 If TE
4 If TE
5 If TE
6 If TE
device actually has two PMD interfaces The Primary PMD Interface and the Alternate PMD Interface
e
e
e
e
e
e
0 and TEL
0 and TEL
1 and OTM and TEL
1 and OTM and TEL
1 and not OTM and TEL
1 and not OTM and TEL
(Continued)
a
can be connected to the PMD and how the Alternate PMD can be enabled
e
e
GND then TXE
V
CC
then TXE
e
e
GND then TXE
V
CC
e
e
GND then TXE
V
102
e
CC
then TXE
e
GND
V
then TXE
CC
Description
e
e
a
GND
V
e
CC
e
device to the Physical Medium Dependant (PMD)
V
GND
CC
a