DP83257VF National Semiconductor, DP83257VF Datasheet - Page 55

• Manufacturer Part Number: DP83257VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83257VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83257VF

Bit
D0
D1
D2
D3
D4
D5
D6
D7
5 0 Registers
5 11 RECEIVE CONDITION REGISTER B (RCRB)
The Receive Condition Register B maintains a historical record of the Lines States recognized by the Receiver Block
When a new Line State is entered the bit corresponding to that line state is set to 1 The bits corresponding to the previous Line
States are not cleared thereby maintaining a record of the Line States detected
The Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition Register B is set to 1 and the corresponding mask bit(s) in Receive Condition Mask Register B (RCMRB) is
also set to 1
ACCESS RULES
Symbol
ILS
ST
ALS
LSUPV
CSE
EBOU
SILS
RES
RES
ADDRESS
D7
0Ah
IDLE LINE STATE Received a minimum of two consecutive Idle symbol pairs (11111 11111)
STATE THRESHOLD This bit will be set to 1 when the internal State Counter reaches zero It will remain set until
a value equal to or greater than one is loaded into the State Threshold Register or State Prescale Threshold
Register and this register is cleared
During the reset process (i e E RST
set to 1
ACTIVE LINE STATE Received a JK symbol pair (11000 10001) and possibly data symbols following
LINE STATE UNKNOWN AND PHY VALID The Receiver Block has not detected the minimum conditions to
enter a known line state
In addition the most recently known line state was either Active Line State or Idle Line State
CONNECTION SERVICE EVENT CASCADE SYNCHRONIZATION ERROR
When one or more bits in the CMT Condition Register (CMTCR) are set and the corresponding bit(s) in the CMT
Condition Mask Register (CMTCMR) are set the Connection service event bit will be set to a 1
When a synchronization error occurs the Cascade Synchronization Error bit is set to 1 A synchronization error
occurs if the Cascade Start signal (CS) is not asserted within approximately 80 ns of Cascade Ready (CR) release
Note Cascade mode and the CMT features can not be used at the same time
Note Cascade mode is only supported on the DP83257 device
ELASTICITY BUFFER UNDERFLOW OVERFLOW The Elasticity Buffer has either overflowed or underflowed
The Elasticity Buffer will automatically recover if the condition which caused the error is only transient but the
event bit will remain set until cleared by software
SUPER IDLE LINE STATE Received a minimum of eight Idle symbol pairs (11111 11111)
RESERVED Reserved for future use
Note Users are discouraged from using these bits The reserved bits are reset to 0 during the reset process They may be set or cleared without
SILS
D6
any effects to the functionality of the PLAYER
(Continued)
Always
READ
EBOU
D5
Conditional
CSE
WRITE
D4
e
GND) since the State Counter is initialized to 0 the State Threshold bit is
a
LSUPV
device
D3
55
Description
ALS
D2
D1
ST
ILS
D0