DP83257VF National Semiconductor, DP83257VF Datasheet - Page 73

• Manufacturer Part Number: DP83257VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83257VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83257VF

Bit
D0
D1
D2
D3
D4
D5
D6
D7
5 0 Registers
5 29 RECEIVE CONDITION COMPARISON REGISTER A (RCCRA)
The Receive Condition Comparison Register A ensures that the Control Bus must first read a bit modified by the PLAYER
device before it can be written to by the Control Bus Interface
The current state of RCRA is automatically written into the Receive Condition Comparison Register A (i e RCCRA
during a Control Bus Interface read cycle of RCRA
During a Control Bus Interface write cycle the PLAYER
Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRA when the value of a bit in RCRA differs
from the value of the corresponding bit in the Receive Condition Comparison Register A
ACCESS RULES
LSUPIC
Symbol
NSDC
QLSC
HLSC
MLSC
NLSC
NTC
LSCC
LSUPIC
D7
ADDRESS
1Ch
NO SIGNAL DETECT COMPARISON The comparison bit for the No Signal Detect bit (NSD) of the Receive
Condition Register A (RCRA)
QUIET LINE STATE COMPARISON The comparison bit for the Quiet Line State bit (QLS) of the Receive
Condition Register A (RCRA)
HALT LINE STATE COMPARISON The comparison bit for the Halt Line State bit (HLS) of the Receive Condition
Register A (RCRA)
MASTER LINE STATE COMPARISON The comparison bit for the Master Line State bit (MLS) of the Receive
Condition Register A (RCRA)
NOISE LINE STATE COMPARISON The comparison bit for the Noise Line State bit (NLS) of the Receive
Condition Register A (RCRA)
NOISE THRESHOLD COMPARISON The comparison bit for the Noise Threshold bit (NT) of the Receive
Condition Register A (RCRA)
LINE STATE CHANGE COMPARISON The comparison bit for the Line State Change bit (LSC) of the Receive
Condition Register A (RCRA)
LINE STATE UNKNOWN AND PHY INVALID COMPARISON The comparison bit for the Line State Unknown
and PHY Invalid bit (LSUPI) of the Receive Condition Register A (RCRA)
LSCC
D6
(Continued)
Always
READ
NTC
D5
NLSC
D4
WRITE
Always
a
MLSC
device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
D3
73
Description
HLSC
D2
QLSC
D1
NSDC
D0
e
RCRA)
a