DP83257VF National Semiconductor, DP83257VF Datasheet - Page 75

• Manufacturer Part Number: DP83257VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83257VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83257VF

D0
D1
D2 –D4
D5
D6
D7
5 0 Registers
5 31 MODE REGISTER 2 (MODE2)
The Mode Register 2 (MODE2) is used to configure the PLAYER
The register is used to software reset the chip setup data parity and enable scrubbing functions
Note This register can not be written to during reset
ACCESS RULES
Bit
ESTC
ADDRESS
D7
1Eh
PHYRST
CBPE
RES
CLKSEL
RES
ESTC
Symbol
RES
D6
PLAYER RESET This bit can be used as a master software reset of the PLAYER function within the
PLAYER
The PLAYER
has been completed
This bit can be set through a C-Bus write but can only be cleared by the PLAYER
C-Bus Parity Enable This bit disables or enables parity checking on C-Bus data When this bit is set to 0 no
parity checking is done When the bit is set to 1 parity checking is enabled during a C-Bus write cycle Should
a mismatch occur the C-Bus Data Parity Error (ICR CPE) bit will be set and the corresponding C-Bus access
is discarded
C-Bus data parity is always generated during a C-Bus read cycle
RESERVED Reserved for future use
CLOCK SELECT This bit controls the frequency of the CLK16 output It resets to 0 which sets the CLK16
output to a 15 625 MHz frequency When set to 1 a 31 25 MHz frequency is generated
Note When the value of this bit is changed no glitches appear on the CLK16 output due to the frequency change
RESERVED Reserved for future use
ENABLE SCRUBBING on TRIGGER CONDITIONS When ESTC is set to 1 and a Trigger Condition occurs
(as set in the TDR register) the Trigger Transition Configuration Register (TTCR) is loaded into the
Configuration Register (CR) and scrubbing is started on all indicate ports that have changed
Scrubbing is accomplished by sending out 2 Phy Invalid symbols followed by ‘‘scrub’’symbol pairs for a time
defined by the Scrub Timer Threshold register
(Continued)
Always
READ
CLKSEL
a
D5
device The clock distribution and recovery sections of the chip are not affected by this reset
a
automatically clears this bit 32 byte time after its assertion to indicate that the reset action
Conditional
RES
WRITE
D4
RES
D3
75
a
Description
device
RES
D2
CBPE
D1
PHYRST
D0
a