DP83950BVQB National Semiconductor, DP83950BVQB Datasheet - Page 62

• Manufacturer Part Number: DP83950BVQB
• Description: IC CTRLR RIC REPEATER 160-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83950BVQB

• Controller Type: Ethernet Repeater Interface Controller
• Interface: IEEE 802.3
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 380mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83950BVQB

Bit
D0
D1
D2
D3
D4
D5
D6
D7
D(7 6)
8 0 RIC Registers
Lower Event Count Mask Register (Page 0H Address 12H)
Upper Event Count Mask Register (Page 0H Address 13H)
Note 1 To count all collisions then both the TXCOLC and RXCOLC bits must be set The OWCC bit should not be set otherwise the port counter will be
incremented twice when an out of collision window collision occurs The OWCC bit alone should be set if only out of window collision are to be counted
Note 2 Writing a 1 enables the event to be counted
Bit
D0
D1
D2
D3
D4
D5
BDLNKC
resv
D7
D7
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
resv
D6
R
R
PARTC
ELBERC
BDLNKC
D6
Symbol
NSFDC
PARTC
PLERC
RECC
JABC
SEC
OWCC
RXCOLC
TXCOLC
Symbol
OWCC
D5
ROR
FWF
resv
resv
RECC
D5
JABBER COUNT ENABLE Enables recording of Jabber Protect events
ELASTICITY BUFFER ERROR COUNT ENABLE Enables recording of Elasticity Buffer Error
events
PHASE LOCK ERROR COUNT ENABLE Enables recording of Carrier Error events
NON SFD COUNT ENABLE Enables recording of Non SFD packet events
SHORT EVENT COUNT ENABLE Enables recording of Short events
RECEIVE COUNT ENABLE Enables recording of Packet Receive (port N status) events that do not
suffer collisions
PARTITION COUNT ENABLE Enables recording of Partition events
BAD LINK COUNT ENABLE Enables recording of Bad Link events
(Continued)
RXCOLC
RESET ON READ This bit selects the action a read operation has upon a port’s event counter
0 No effect upon register contents
1 The counter register is reset
FREEZE WHEN FULL This bit controls the freezing of the Event Count registers when the
counter is full (FFFF Hex)
RESERVED FOR FUTURE USE This bit should be written with a low logic level
TRANSMIT COLLISION COUNT ENABLE Enables recording of transmit collision events only
RECEIVE COLLISION COUNT ENABLE Enables recording of receive collision events only
OUT OF WINDOW COLLISION COUNT ENABLE Enables recording of out of window collision
events only
RESERVED FOR FUTURE USE These bits should be written with a low logic level
SEC
D4
D4
NSFDC
D3
TXCOLC
D3
PLERC
D2
resv
D2
ELBER C
62
D1
FWF
D1
Description
JABC
ROR
Description
D0
D0