DP83950BVQB National Semiconductor, DP83950BVQB Datasheet - Page 65

• Manufacturer Part Number: DP83950BVQB
• Description: IC CTRLR RIC REPEATER 160-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83950BVQB

• Controller Type: Ethernet Repeater Interface Controller
• Interface: IEEE 802.3
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 380mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83950BVQB

Bit
D0
D1
D2
D3
D4
D5
D6
D7
8 0 RIC Registers
RIC Address Register (Page 0H Address 17H)
This register may be used to differentiate between RICs in a multi-RIC repeater system The contents of this register form part of
the information available through the management bus
Packet Compress Decode Register (Page 0H Address 18H)
This register is used to determine the number of bytes in the data field of a packet which are transferred over the management
bus when the packet compress option is employed The register bits perform the function of a direct binary decode Thus up to
255 bytes of data may be transferred over the management bus if packet compression is selected
Inter Frame Gap Threshold Select Register (Page 0H Address 1FH)
This register is used to configure the hub management interface to provide a certain minimum inter frame gap between packets
transmitted over the management bus The value written to this register plus one is the magnitude in bit times of the minimum
IFG allowed on the management bus
Port Event Record Registers (Page 1H Address 11H to 1DH)
These registers hold the recorded events for the specified RIC port The flags are cleared when the register is read
Port Event Count Register (Pages 2H and 3H)
The Event Count (EC) register shows the instantaneous value of the specified port’s 16-bit counter The counter increments
when an enabled event occurs The counter may be cleared when it is read and prevented from rolling over when the maximum
count is reached by setting the appropriate control bits in the Upper Event Count mask register Since the RIC’s processor port
is octal and the counters are 16 bits long a temporary holding register is employed for register reads When one of the counters
is read either high or low byte first all 16 bits of the counter are transferred to a holding register Provided the next read cycle to
the counter array accesses the same counter’s other byte then the read cycle accesses the holding register This avoids the
problem of events occurring in between the two processor reads and indicating a false count value In order to enter a new value
to the holding register a different counter must be accessed or the same counter byte must be re-read
Lower Byte
Upper Byte
IFGT7
PCD7
BDLNK
EC15
EC7
D7
A5
D7
D7
D7
D7
D7
R W
R
R
R
R
R
R
R
R
IFGT6
PCD6
EC14
EC6
D6
A4
D6
D6
D6
PART
D6
Symbol
BDLNK
D6
ELBER
NSFD
PART
PLER
OWC
JAB
SE
IFGT5
PCD5
EC5
EC13
D5
A3
D5
D5
D5
OWC
D5
D5
JABBER A Jabber Protect event has occurred
ELASTICITY BUFFER ERROR A Elasticity Buffer Error has occurred
PHASE LOCK ERROR A Phase Lock Error event has occurred
NON SFD A Non SFD packet event has occurred
SHORT EVENT A Short event has occurred
OUT OF WINDOW COLLISION An out of window collision event has occurred
PARTITION A partition event has occurred
BAD LINK A link failure event has occurred
(Continued)
IFGT4
PCD4
EC4
D4
EC12
A2
D4
D4
D4
D4
SE
D4
NSFD
IFGT3
PCD3
EC3
D3
D3
A1
D3
D3
D3
EC11
D3
IFGT2
PLER
PCD2
EC2
D2
A0
D2
D2
D2
D2
EC10
D2
65
IFGT1
ELBER
PCD1
EC1
res
D1
D1
D1
D1
D1
EC9
D1
Description
IFGT0
PCD0
EC0
res
EC8
D0
D0
D0
D0
JAB
D0
D0