LAN8700IC-AEZG SMSC, LAN8700IC-AEZG Datasheet - Page 31

• Manufacturer Part Number: LAN8700IC-AEZG
• Description: TXRX ETHERNET 10/100 IND 36-QFN
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8700IC-AEZG

• Protocol: MII, RMII
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Supply Voltage Range: 3V To 3.6V
• Digital Ic Case Style: QFN
• No. Of Pins: 36
• Operating Temperature Range: -40°C To +85°C
• Control Interface: MII, RMII
• Data Rate Max: 100Mbps
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 638-1047-6

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
Datasheet
SMSC LAN8700/LAN8700i
4.10
4.11
4.12
4.12.1
The nINT, TX_ER, and TXD4 functions share a common pin. There are two functional modes for this
pin, the TX_ER/TXD4 mode and nINT (interrupt) mode. The RXD3/nINTSEL pin is used to select one
of these two functional modes.
The RXD3/nINTSEL pin is latched on the rising edge of the nRST. The system designer must float the
nINTSEL pin to put the nINT/TX_ER/TXD4 pin into nINT mode or pull-low to VSS with an external
resistor (see
TX_ER/TXD4 mode. The default setting is to float the pin high for nINT mode.
The PHY ADDRESS bits are latched on the rising edge of the internal reset (nRESET). The 5-bit
address word[0:4] is input on the PHYAD[0:4] pins. The default setting is all high 5'b1_1111.
The address lines are strapped as defined in the diagram below. The LED outputs will automatically
change polarity based on the presence of an external pull-down resistor. If the LED pin is pulled high
(by an internal 100K pull-up resistor) to select a logical high PHY address, then the LED output will
be active low. If the LED pin is pulled low (by an external pull-down resistor (see
Strapping Configuration Resistors,” on page
will then be an active high output.
To set the PHY address on the LED pins without LEDs or on the CRS pin, float the pin to set the
address high or pull-down the pin with an external resistor (see
Configuration Resistors,” on page
Strapping on LED’s":
The Digital I/O pins on the LAN8700/LAN8700i are variable voltage to take advantage of low power
savings from shrinking technologies. These pins can operate from a low I/O voltage of +1.8V-10% up
to +3.3V+10%. Due to this low voltage feature addition, the system designer needs to take
consideration as for two aspects of their design. Boot strapping configuration and I/O voltage stability.
Boot Strapping Configuration
Due to a lower I/O voltage, a lower strapping resistor needs to be used to ensure the strapped
configuration is latched into the PHY device at power-on reset.
nINT/TX_ER/TXD4 Strapping
PHY Address Strapping and LED Output Polarity Selection
Variable Voltage I/O
LED output = active low
Table 4.3, “Boot Strapping Configuration Resistors,” on page
Phy Address = 1
Figure 4.5 PHY Address Strapping on LED’s
VDD
~270 ohms
32) to GND to set the address low. See Figure 4.5, "PHY Address
DATASHEET
LED1-LED4
®
31
Technology in a Small Footprint
32) to select a logical low PHY address, the LED output
~10K ohms
LED output = active high
Phy Address = 0
Table 4.3, “Boot Strapping
~270 ohms
32) to set the device in
Revision 2.2 (12-04-09)
LED1-LED4
Table 4.3, “Boot