LAN8700IC-AEZG SMSC, LAN8700IC-AEZG Datasheet - Page 53

• Manufacturer Part Number: LAN8700IC-AEZG
• Description: TXRX ETHERNET 10/100 IND 36-QFN
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8700IC-AEZG

• Protocol: MII, RMII
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Supply Voltage Range: 3V To 3.6V
• Digital Ic Case Style: QFN
• No. Of Pins: 36
• Operating Temperature Range: -40°C To +85°C
• Control Interface: MII, RMII
• Data Rate Max: 100Mbps
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 638-1047-6

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
Datasheet
SMSC LAN8700/LAN8700i
5.4.8.3
5.4.9
5.4.9.1
Ethernet
Ethernet
10/100
10/100
MAC
MAC
data that is received from the link partner on the MDI is looped back out to the link partner. The digital
interface signals on the local MAC interface are isolated.
Connector Loopback
The LAN8700/LAN8700i maintains reliable transmission over very short cables, and can be tested in
a connector loopback as shown in
transmit signals an the output of the transformer back to the receiver inputs, and this loopback will
work at both 10 and 100.
Configuration Signals
The PHY has 11 configuration signals whose inputs should be driven continuously, either by external
logic or external pull-up/pull-down resistors.
Physical Address Bus - PHYAD[4:0]
The PHYAD[4:0] signals are driven high or low to give each PHY a unique address. This address is
latched into an internal register at end of hardware reset. In a multi-PHY application (such as a
repeater), the controller is able to manage each PHY via the unique address. Each PHY checks each
management data frame for a matching address in the relevant bits. When a match is recognized, the
PHY responds to that particular frame. The PHY address is also used to seed the scrambler. In a multi-
TXD
TXD
RXD
RXD
X
X
Digital
Digital
Ethernet Transceiver
Ethernet Transceiver
Figure 5.4 Connector Loopback Block Diagram
Far-end system
Figure 5.3 Far Loopback Block Diagram
SMSC
SMSC
Analog
Analog
DATASHEET
Figure
®
53
Technology in a Small Footprint
5.4. An RJ45 loopback cable can be used to route the
TX
RX
TX
RX
XFMR
XFMR
RJ45 Loopback Cable.
Created by connecting pin 1 to pin 3
and connecting pin 2 to pin 6.
CAT-5
1
2
3
4
5
6
7
8
Revision 2.2 (12-04-09)
Partner
Link