LAN8700IC-AEZG SMSC, LAN8700IC-AEZG Datasheet - Page 32

• Manufacturer Part Number: LAN8700IC-AEZG
• Description: TXRX ETHERNET 10/100 IND 36-QFN
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8700IC-AEZG

• Protocol: MII, RMII
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Supply Voltage Range: 3V To 3.6V
• Digital Ic Case Style: QFN
• No. Of Pins: 36
• Operating Temperature Range: -40°C To +85°C
• Control Interface: MII, RMII
• Data Rate Max: 100Mbps
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 638-1047-6

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Revision 2.2 (12-04-09)
4.12.2
4.13
4.13.1
I/O voltage
3.0 to 3.6
2.0 to 3.0
1.6 to 2.0
I/O Voltage Stability
The I/O voltage the System Designer applies on VDDIO needs to maintain its value with a tolerance
of ± 10%. Varying the voltage up or down, after the PHY has completed power-on reset can cause
errors in the PHY operation.
The Management Control module includes 3 blocks:
Serial Management Interface (SMI)
The Serial Management Interface is used to control the LAN8700/LAN8700i and obtain its status. This
interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as
“vendor-specific” registers 16 to 31 allowed by the specification. Non-supported registers (7 to 15) will
be read as hexadecimal “FFFF”.
At the system level there are 2 signals, MDIO and MDC where MDIO is bi-directional open-drain and
MDC is the clock.
A special feature (enabled by register 17 bit 3) forces the PHY to disregard the PHY-Address in the
SMI packet causing the PHY to respond to any address. This feature is useful in multi-PHY
applications and in production testing, where the same register can be written in all the PHYs using a
single write transaction.
The MDC signal is an aperiodic clock provided by the station management controller (SMC). The MDIO
signal receives serial data (commands) from the controller SMC, and sends serial data (status) to the
SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time between
edges.
The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400
ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a
microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in
The timing relationships of the MDIO signals are further described in
Interface (SMI) Timing," on page
PHY Management Control
Serial Management Interface (SMI)
Management Registers Set
Interrupt
Table 4.3 Boot Strapping Configuration Resistors
Figure 4.6
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
55.
and
DATASHEET
Figure
32
4.7.
Pull-up/Pull-down Resistor
7.5k ohm resistor
10k ohm resistor
5k ohm resistor
Section 6.1, "Serial Management
SMSC LAN8700/LAN8700i
®
Technology in a Small Footprint
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