LAN8700IC-AEZG SMSC, LAN8700IC-AEZG Datasheet - Page 48

• Manufacturer Part Number: LAN8700IC-AEZG
• Description: TXRX ETHERNET 10/100 IND 36-QFN
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8700IC-AEZG

• Protocol: MII, RMII
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Supply Voltage Range: 3V To 3.6V
• Digital Ic Case Style: QFN
• No. Of Pins: 36
• Operating Temperature Range: -40°C To +85°C
• Control Interface: MII, RMII
• Data Rate Max: 100Mbps
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 638-1047-6

a.
Revision 2.2 (12-04-09)
5.3
5.3.1
Mask
30.7
30.6
30.5
30.4
30.3
30.2
30.1
If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high, nINT will assert for
256 ms, approximately one second after ENERGYON goes low when the Cable is unplugged. To prevent an
unexpected assertion of nINT, the ENERGYON interrupt mask should always be cleared as part of the
ENERGYON interrupt service routine.
29.7
29.6
29.5
29.4
29.3
29.2
29.1
The Management interface supports an interrupt capability that is not a part of the IEEE 802.3
specification. It generates an active low asynchronous interrupt signal on the nINT output whenever
certain events are detected as setup by the Interrupt Mask Register 30.
The Interrupt system on the SMSC LAN8700/8700I has two modes, a Primary Interrupt mode and an
Alternative Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask
bit is set, the difference is how they de-assert the output interrupt signal nINT.
The Primary interrupt mode is the default interrupt mode after a power-up or hard reset, the Alternative
interrupt mode would need to be setup again after a power-up or hard reset.
Primary Interrupt System
The Primary Interrupt system is the default interrupt mode, (Bit 17.6 = ‘0’). The Primary Interrupt
System is always selected after power-up or hard reset.
To set an interrupt, set the corresponding mask bit in the interrupt Mask register 30 (see
Then when the event to assert nINT is true, the nINT output will be asserted.
When the corresponding Event to De-Assert nINT is true, then the nINT will be de-asserted.
Note: The ENERGYON bit 17.1 is defaulted to a ‘1’ at the start of the signal acquisition process,
Interrupt Management
Interrupt Source Flag
Parallel Detection Fault
Remote Fault Detected
Auto-Negotiation Page
Auto-Negotiation LP
Auto-Negotiation
Acknowledge
ENERGYON
therefore the Interrupt source flag 29.7 will also read as a ‘1’ at power-up. If no signal is
present, then both 17.1 and 29.7 will clear within a few milliseconds.
Link Down
Received
complete
Table 5.46 Interrupt Management Table.
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
17.1
5.14
1.5
1.4
1.2
6.4
6.1
Interrupt Source
DATASHEET
Parallel Detection
Page Received
Auto-Negotiate
Remote Fault
Acknowledge
ENERGYON
Link Status
Complete
Fault
48
Event to Assert nINT
Rising 17.1
Rising 5.14
Falling 1.2
Rising 1.5
Rising 1.4
Rising 6.4
Rising 6.1
a
SMSC LAN8700/LAN8700i
Event to De-Assert nINT
Reading register 29 or
Reading register 6, or
Reading register 6, or
Re-Auto Negotiate, or
Reading register 1 or
Reading register 1 or
Re-Auto Negotiate or
Reading register 29
Reading register 29
Reading register 29
Reading register 29
Reading register 29
Read register 29
®
Falling of 6.1 or
Falling 17.1 or
Falling 5.14 or
Falling 1.4, or
Technology in a Small Footprint
Falling 1.5 or
Falling 6.4 or
Link Down.
Link down
Table
Datasheet
5.46).