ICS1893YI-10LFT IDT, Integrated Device Technology Inc, ICS1893YI-10LFT Datasheet - Page 40

• Manufacturer Part Number: ICS1893YI-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893YI-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893YI-10LFT

6.1 Functional Block: Media Independent Interface
ICS1893Y-10 Rev F 1/20/04
All ICS1893Y-10 MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the
ICS1893Y-10 MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz
(for 10Base-T operations).
The Media Independent Interface (MII) consists of two primary components:
1. An interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893Y-10).
2. An interface between the PHY (the ICS1893Y-10) and an STA (Station Management entity). The
The ICS1893Y-10 Management Register set (discussed in
consists of the following:
•
•
•
Basic Management registers.
As defined in the ISO/IEC 8802-3 standard, these registers include the following:
Extended Management registers.
As defined in the ISO/IEC 8802-3 standard, the ICS1893Y-10 supports Extended registers that provide
access to the Organizationally Unique Identifier and all auto-negotiation functionality.
ICS (Vendor-Specific) Management registers.
The ICS1893Y-10 provides vendor-specific registers for enhanced PHY operations. Among these is the
QuickPoll Detailed Status Register that provides a comprehensive and consolidated set of real-time PHY
information. Reading the QuickPoll register enables the MAC to obtain comprehensive status data with a
single register access.
– Control Register (register 0), which handles basic device configuration
– Status Register (register 1), which reports basic device capabilities and status
This MAC-PHY part of the MII consists of three subcomponents:
a. A synchronous Transmit interface that includes the following signals:
b. A synchronous Receive interface that includes the followings signals:
c. A Media Status or Control interface that consists of a Carrier Sense signal (CRS) and a Collision
STA-PHY part of the MII is a two-wire, Serial Management Interface that consists of the following:
a. A clock (MDC)
b. A synchronous, bi-directional data signal (MDIO) that provides an STA with access to the
ICS1893Y-10 Data Sheet - Release
Detection signal (COL).
ICS1893Y-10 Management Register set
(1) A data nibble, TXD[3:0]
(2) An error indicator, TXER
(3) A delimiter, TXEN
(4) A clock, TXCLK
(1) A data nibble, RXD[3:0]
(2) An error indicator, RXER
(3) A delimiter, RXDV
(4) A clock, RXCLK
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
40
Chapter 7, “Management Register
Chapter 6 Functional Blocks
January, 2004
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