ICS1893YI-10LFT IDT, Integrated Device Technology Inc, ICS1893YI-10LFT Datasheet - Page 95

• Manufacturer Part Number: ICS1893YI-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893YI-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893YI-10LFT

7.12.6 False Carrier (bit 17.8)
7.12.7 Invalid Symbol (bit 17.7)
7.12.8 Halt Symbol (bit 17.6)
7.12.9 Premature End (bit 17.5)
ICS1893Y-10 Rev F 1/20/04
The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893Y-10 in 100Base
mode.
A False Carrier occurs when the ICS1893Y-10 begins evaluating potential data on the incoming 100Base
data stream, only to learn that it was not a valid /J/K/. If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
Note:
The Invalid Symbol bit indicates to an STA the detection of an Invalid Symbol in a 100Base data stream by
the ICS1893Y-10.
When the ICS1893Y-10 is receiving a packet, it examines each received Symbol to ensure the data is error
free. If an error occurs, the port indicates this condition to the MAC/repeater by asserting the RXER signal.
In addition, the ICS1893Y-10 sets its Invalid Symbol bit to logic one. Therefore, if this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
Note:
The Halt Symbol bit indicates to an STA the detection of a Halt Symbol in a 100Base data stream by the
ICS1893Y-10.
During reception of a valid packet, the ICS1893Y-10 examines each symbol to ensure that the data being
passed to the MAC/Repeater Interface is error free. In addition, it looks for special symbols such as the Halt
Symbol. If a Halt Symbol is encountered, the ICS1893Y-10 indicates this condition to the MAC/repeater.
If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
Note:
The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream
by the ICS1893Y-10.
During reception of a valid packet, the ICS1893Y-10 examines each symbol to ensure that the data being
passed to the MAC/Repeater Interface is error free. If two consecutive Idles are encountered, it indicates
this condition to the MAC/repeater by setting this bit.
Zero, it indicates a False Carrier has not been detected since either the last read or reset of this register.
One, it indicates a False Carrier was detected since either the last read or reset of this register.
Zero, it indicates an Invalid Symbol has not been detected since either the last read or reset of this
register.
One, it indicates an Invalid Symbol was detected since either the last read or reset of this register.
Zero, it indicates a Halt Symbol has not been detected since either the last read or reset of this register.
One, it indicates a Halt Symbol was detected in the packet since either the last read or reset of this
register.
ICS1893Y-10 - Release
This bit has no definition in 10Base-T mode.
This bit has no definition in 10Base-T mode.
This bit has no definition in 10Base-T mode.
and
and
and
Copyright © 2004, Integrated Circuit Systems, Inc.
Section 7.1.4.2, “Latching Low
Section 7.1.4.2, “Latching Low
Section 7.1.4.2, “Latching Low
All rights reserved.
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Bits”.)
Bits”.)
Bits”.)
Chapter 7 Management Register Set
January, 2004
Section
Section
Section