ICS1893YI-10LFT IDT, Integrated Device Technology Inc, ICS1893YI-10LFT Datasheet - Page 70

• Manufacturer Part Number: ICS1893YI-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893YI-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893YI-10LFT

7.3.2 100Base-TX Full Duplex (bit 1.14)
7.3.3 100Base-TX Half Duplex (bit 1.13)
7.3.4 10Base-T Full Duplex (bit 1.12)
7.3.5 10Base-T Half Duplex (bit 1.11)
ICS1893Y-10 Rev F 1/20/04
The STA reads this bit to learn if the ICS1893Y-10 can support 100Base-TX, full-duplex operations. The
ISO/IEC specification requires that the ICS1893Y-10 must set bit 1.14 to logic:
•
•
Bit 1.14 is a Command Override Write bit, which allows an STA to alter the default value of this bit. [See the
description of bit 16.15, the Command Override Write Enable bit, in
Control
The STA reads this bit to learn if the ICS1893Y-10 can support 100Base-TX, half-duplex operations. The
ISO/IEC specification requires that the ICS1893Y-10 must set bit 1.13 to logic:
•
•
This bit 1.13 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in
Extended Control
The STA reads this bit to learn if the ICS1893Y-10 can support 10Base-T, full-duplex operations. The
ISO/IEC specification requires that the ICS1893Y-10 must set bit 1.12 to logic:
•
•
This bit 1.12 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in
Extended Control
The STA reads this bit to learn if the ICS1893Y-10 can support 10Base-T, half-duplex operations. The
ISO/IEC specification requires that the ICS1893Y-10 must set bit 1.11 to logic:
•
•
Bit 1.11 of the ICS1893Y-10 Status Register is a Command Override Write bit., which allows an STA to alter
the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in
Section 7.11, “Register 16: Extended Control
Zero if it cannot support 100Base-TX, full-duplex operations.
One if it can support 100Base-TX, full-duplex operations. (For the ICS1893Y-10, the default value of bit
1.14 is logic one, in that the ICS1893Y-10 supports 100Base-TX, full-duplex operations.)
Zero if it cannot support 100Base-TX, half-duplex operations.
One if it can support 100Base-TX, half-duplex operations. (For the ICS1893Y-10, the default value of bit
1.13 is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the
ICS1893Y-10 supports 100Base-TX, half-duplex operations.)
Zero if it cannot support 10Base-T, full-duplex operations.
One if it can support 10Base-T, full-duplex operations. (For the ICS1893Y-10, the default value of bit 1.12
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the
ICS1893Y-10 supports 10Base-T, full-duplex operations.)
Zero if it cannot support 10Base-T, half-duplex operations.
One if it can support 10Base-T, half-duplex operations. (For the ICS1893Y-10, the default value of bit
1.11 is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the
ICS1893Y-10 supports 10Base-T, half-duplex operations.)
ICS1893Y-10 Data Sheet - Release
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Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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70
Section 7.11, “Register 16: Extended
Chapter 7 Management Register Set
Section 7.11, “Register 16:
Section 7.11, “Register 16:
January, 2004