PEB24911HV13 Lantiq, PEB24911HV13 Datasheet - Page 119

• Manufacturer Part Number: PEB24911HV13
• Manufacturer: Lantiq

Specifications of PEB24911HV13

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PEF 24911
Operational Description
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
0001 (INTEST) is the default value of the instruction register.
SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is
used to preload (TDI) / shift out (TDO) the boundary scan with a test vector. Both
activities are transparent to the system functionality.
IDCODE Register
The 32-bit identification register is serially read out via TDO. It contains the version
number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB
is fixed to "1".
Version
Device Code
Manufacturer Code
Output
0001
0000 0000 0111 0010
0000 1000 001
1
-->
TDO
Note: In the state "test logic reset" the code "0011" is loaded into the instruction code
register.
CLAMP allows the state of the signals included in the boundary scan driven from the
PEF 24911 to be determined from the boundary scan register while the bypass register
is selected as the serial path between TDI and TDO. These output signals driven from
the DFE-Q V2.1 will not change while CLAMP is selected.
HIGHZ sets all output pins included to the boundary scan path into a high impedance
state. In this state, an in-circuit test system may drive signals onto the connections
normally driven by the DFE-Q V2.1 outputs without incurring the risk of damage to the
DFE-Q V2.1.
BYPASS, a bit entering TDI is shifted to TDO after one TCK clock cycle, e.g. to skip
testing of selected ICs on a printed circuit board.
Data Sheet
109
2001-07-16