PSF21150FV14XP Infineon Technologies, PSF21150FV14XP Datasheet - Page 111

• Manufacturer Part Number: PSF21150FV14XP
• Manufacturer: Infineon Technologies

Specifications of PSF21150FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

S Interface
Data which is read from and written to the IOM-2 interface by the B-channel controller as
described in the previous chapter is received from and transmitted to the S interface
(Figure
.
Figure 61
As the timeslot structure of the IOM-2 interface is different from the S interface, it is
important to consider the delay and mapping of data between both interfaces.
Figure 61
s. Serial data from the FIFO is mapped to the corresponding B- and D-channel timeslots
on IOM-2.
The ITU I.430 specifies the order and timeslot position of B- and D-channel data on the
S-frame. Due to that the order of B- and D-channel data on S is different from IOM-2
which has the effect that mapping of data from IOM-2 to S will change the original order
of the serial data stream. However, this has no effect as the remote receiver is using the
same mechanism for mapping data between S and IOM-2. In IPAC-X B- and D-channel
bits of one IOM-frame are mapped to the corresponding timeslots of the same S-frame.
.
Figure 62
Data Sheet
Serial data in FIFO
Mapping of serial
data on IOM-2
Mapping from
IOM-2 to S
61).
B-channel
HDLC 1
TX/RX FIFOs
shows the example for bundling 2B+D channels for transmission of 144 kbit/
Timeslot Assignment on S
Mapping of Bits from IOM-2 to S
1
1
1
2
2
2
B-channel
HDLC 2
TX/RX FIFOs
3
3
3
Host
4
4
4
B1
B1
5
5
5
IOM-2 Interface
6
6
6
D-channel
HDLC
TX/RX FIFOs
7
7
7
8
8
8
9
9
Mapping of data between IOM-2 and S-interface
(described in this chapter)
17
111
D
10
10
11
11
9
12
12
B2
10
13
13
Description of Functional Blocks
S transceiver
11
14
14
12
B2
15
15
13
16
16
14
17
15
17
18
D
16
PSB/PSF 21150
18
19
S
20
18
D
Next FSC-frame
2003-01-30
IPAC-X