MAX9268GCM/V+ Maxim Integrated Products, MAX9268GCM/V+ Datasheet - Page 14

• Manufacturer Part Number: MAX9268GCM/V+
• Description: IC SERIALIZER GMSL LVDS 48TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9268GCM/V+

• Function: Deserializer
• Data Rate: 2.5Gbs
• Input Type: Serial
• Output Type: LVDS
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Outputs: -
• Number Of Inputs: -

Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
Table 1. Power-Up Default Register Map (see Table 12) (continued)
14
REGISTER
ADDRESS
_____________________________________________________________________________________
(hex)
0x0A
0x0B
0x0C
0x0D
0x04
0x05
0x06
0x07
0x08
0x09
0x0E
0x12
0x13
0x14
0x03 or 0x13
0x24 or 0x29
POWER-UP
(read only)
(read only)
DEFAULT
(hex)
0xC8
0x0F
0x54
0x30
0x12
0x20
0x00
0x00
0x00
0x00
0xX0
0x01
LOCKED = 0, LOCK output is low (read only)
OUTENB = 0, outputs enabled
PRBSEN = 0, PRBS test disabled
SLEEP = 0 or 1, SLEEP setting default depends on CDS and MS pin state at power-up
(see the Link Startup Procedure section)
INTTYPE = 00, base mode uses I
REVCCEN = 1, reverse control channel active (sending)
FWDCCEN = 1, forward control channel active (receiving)
I2CMETHOD = 0, I
HPFTUNE = 01, 3.75MHz equalizer highpass cutoff frequency
PDHF = 0, high-frequency boosting disabled
EQTUNE = 0100 (EQS = high, 5.2dB), EQTUNE = 1001 (EQS = low, 10.7dB), EQTUNE
default setting depends on EQS pin state at power-up
RESERVED = 0
AUTORST = 0, error registers/output autoreset disabled
DISINT = 0, INT transmission enabled
INT = 0, INT output is low (read only)
GPIO1OUT = 1, GPIO1 output set to high
GPIO1 = 1, GPIO1 input = high (read only)
GPIO0OUT = 1, GPIO0 output set to high
GPIO0 = 1, GPIO0 input = high (read only)
RESERVED = 01010100
RESERVED = 00110000
RESERVED = 11001000
RESERVED = 00010010
RESERVED = 00100000
ERRTHR = 00000000, error threshold set to zero for decoding errors
DECERR = 00000000, zero decoding errors detected
PRBSERR = 00000000, zero PRBS errors detected
MCLKSRC = 0, MCLK is derived from PCLK (see Table 5)
MCLKDIV = 0000000, MCLK output is disabled
RESERVED = XXX
RESERVED = 10000
RESERVED = 00
FORCELVDS = 0, normal LVDS operation
DCS = 0, normal CMOS driver current strength
DISCNTL1 = 0, serial-data bit 27 is mapped to CNTL1
DISRES = 0, serial-data bit 27 is mapped to RES
ILVDS = 01, 3.5mA LVDS output current
2
C master sends the register address
POWER-UP DEFAULT SETTINGS
2
C
(MSB FIRST)