MAX9268GCM/V+ Maxim Integrated Products, MAX9268GCM/V+ Datasheet - Page 20

• Manufacturer Part Number: MAX9268GCM/V+
• Description: IC SERIALIZER GMSL LVDS 48TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9268GCM/V+

• Function: Deserializer
• Data Rate: 2.5Gbs
• Input Type: Serial
• Output Type: LVDS
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Outputs: -
• Number Of Inputs: -

Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
The control channel is available for the FC to send and
receive control data over the serial link simultaneously with
the high-speed data, to program registers on the link serial-
izer/deserializer or to program peripherals. Configuring the
CDS pin allows a FC to control the link from the side of the
serializer or deserializer, or with dual FCs from both sides,
to support a wide variety of applications.
The control channel runs in base mode or bypass mode
according to the mode-selection (MS) input of the device
connected to the FC. In base mode, the control-channel
transactions are half-duplex and in bypass mode they are
full-duplex.
In base mode the FC is the host, and in order to access the
registers of the serializer or deserializer it must use the
GMSL UART format and protocol. The FC accesses
peripherals with an I
packets, which are converted to I
or deserializer on the remote side of the link. The FC
communicates with a UART peripheral in base mode
(through INTTYPE register settings) using the GMSL UART
protocol. The device addresses of the GMSL serializer and
MAX9268 in base mode are programmable. The default
MAX9268 device address is determined by ADD0 and
ADD1 upon power-up, or after returning from a power-
down state (Table 2).
When the peripheral interface uses I
serializer/MAX9268 convert packets to I
addresses different from those of the GMSL serializer or
MAX9268. The converted I
original UART bit rate.
The GMSL serializer embeds control signals going to the
MAX9268 in the high-speed forward link. The MAX9268
uses a proprietary differential line coding to send signals
20
Figure 16. GMSL UART Protocol for Base Mode
Control Channel and Register Programming
_____________________________________________________________________________________
2
C interface by sending GMSL UART
SYNC
SYNC
2
C bit rate is the same as the
DEV ADDR + R/W
DEV ADDR + R/W
2
C (default), the GMSL
2
C by the serializer
2
MASTER WRITES TO SLAVE
C that have device
REG ADDR
REG ADDR
Base Mode
MASTER WRITES TO SLAVE
NUMBER OF BYTES
NUMBER OF BYTES
READ DATA FRMAT
WRITE DATA FORMAT
back towards the serializer. The speed of the control chan-
nel ranges from 100kbps to 1Mbps in both directions. The
GMSL serializer and MAX9268 deserializer automatically
detect the control-channel bit rate in base mode. Packet bit
rates can vary up to 3.5x from the previous bit rate (see the
Changing the Clock Frequency section). Figure 16 shows
the UART protocol for writing and reading in base mode
between the FC and the GMSL serializer/MAX9268.
Figure 17 shows the UART data format. Figures 18 and 19
detail the formats of the SYNC byte (0x79) and the ACK
byte (0xC3). The FC and the connected slave chip gen-
erate the SYNC byte and ACK byte, respectively. Events
such as device wake-up and interrupt generate transitions
on the control channel that should be ignored by the FC.
Data written to the GMSL serializer/MAX9268 registers do
not take effect until after the acknowledge byte is sent.
This allows the FC to verify write commands received with-
out error, even if the result of the write command directly
affects the serial link. The slave uses the SYNC byte to
synchronize with the host UART data rate automatically. If
the INT or MS inputs of the MAX9268 toggle while there is
control-channel communication, the control-channel com-
munication can be corrupted since INT has priority on the
control channel. In the event of a missed acknowledge, the
FC should assume there was an error in the packet when
the slave device receives it, or that an error occurred during
the response from the slave device. In base mode, the FC
must keep the UART Tx/Rx lines high for 16 bit times before
sending a new packet.
As shown in Figure 20, the remote-side device converts
the packets going to or coming from the peripherals from
the UART format to the I
remote device removes the byte number count and adds or
receives the ACK between the data bytes of I
data rate is the same as the UART data rate.
MASTER READS FROM SLAVE
BYTE 1
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
2
C format and vice versa. The
BYTE N
ACK
2
C. The I
2
C’s