TB28F004S3-150 Intel, TB28F004S3-150 Datasheet - Page 13

• Manufacturer Part Number: TB28F004S3-150
• Manufacturer: Intel

Specifications of TB28F004S3-150

• Density: 4Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

0FFFFF
07FFFF
01FFFF
00FFFF
Figure 6. Device Identifier Code Memory Map
1FFFFF
1F0002
1F0000
0F0002
0F0000
070002
070000
010002
010000
000003
000002
000001
000000
PRELIMINARY
Block 31 Lock Configuration
Block 0 Lock Configuration
Block 15 Lock Configuration
Block 7 Lock Configuration
Master Lock Configuration
Block 1 Lock Configuration
(Blocks 16 through 30)
(Blocks 8 through 14)
(Blocks 2 through 14)
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Manufacturer Code
Device Code
Reserved for
Reserved for
Reserved for
Reserved for
Reserved for
Reserved for
Reserved for
Reserved For
Reserved for
Block 31
Block 15
Block 1
Block 7
Block 0
4-Mbit
8-Mbit
16-Mbit
3.5
The read identifier codes operation outputs the
manufacturer code,
configuration codes for each block, and master lock
configuration code (see Figure 6). Using the
manufacturer and device codes, the system
software can automatically match the device with its
proper algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
3.6
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active
and OE# = V
execute a command are latched on the rising edge
of WE# or CE# (whichever goes high first).
Standard microprocessor write timings are used.
Figure 18 illustrates a write operation.
4.0
When the V
from the status register, identifier codes, or blocks
are enabled. Placing V
successful block erase, program, and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
COMMAND DEFINITIONS
Read Identifier Codes
Operation
Write
PP
IH
28F004S3/28F008S3/28F016S3
. The address and data needed to
voltage
device code,
PPH1/2
V
PPLK
, read operations
on V
PP
block
enables
lock
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