TB28F004S3-150 Intel, TB28F004S3-150 Datasheet - Page 27

• Manufacturer Part Number: TB28F004S3-150
• Manufacturer: Intel

Specifications of TB28F004S3-150

• Density: 4Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

5.0
5.1
Intel provides three control inputs to accommodate
multiple memory connections: CE#, OE#, and RP#.
Three-line control provides for:
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while de-
selected memory devices are in standby mode.
RP#
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase program
and lock-bit configuration completion. This output
can be directly connected to an interrupt input of
the system CPU. RY/BY# transitions low when the
WSM is busy and returns to V
executing the internal algorithm. During suspend
and deep power-down modes, RY/BY# remains at
V
5.3
Flash memory power switching characteristics
require
designers are interested in three supply current
issues: standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Two-line control and proper
decoupling
transient voltage peaks. Each device should have a
0.1 µF ceramic capacitor connected between its
V
These high-frequency, low-inductance capacitors
should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7 µF
electrolytic capacitor should be placed at the array’s
power supply connection between V
The bulk capacitor will overcome voltage slumps
caused by PC board trace inductance.
OH
CC
PRELIMINARY
a. Lowest possible memory power dissipation.
b. Data bus contention avoidance.
.
and GND and between its V
should
DESIGN CONSIDERATIONS
Three-Line Output Control
RY/BY# Hardware Detection
Power Supply Decoupling
careful
capacitor
be
device
connected
selection
decoupling.
OH
when it is finished
to
will
PP
CC
the
and GND.
and GND.
suppress
System
system
5.4
Updating flash memories that reside in the target
system requires that the printed circuit board
designer pay attention to the V
trace. The V
for byte writing and block erasing. Use similar trace
widths and layout considerations given to the V
power bus. Adequate V
decoupling will decrease V
overshoots.
5.5
Block erase, program and lock-bit configuration are
not guaranteed if V
voltage
RP#
register bit SR.3 is set to “1” along with SR.4 or
SR.5, depending on the attempted operation. If RP#
transitions to V
lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation
will abort and the device will enter deep power-
down. The aborted operation may leave data
partially altered. Therefore, the command sequence
must be repeated after normal operation is
restored.
5.6
The device is designed to offer protection against
accidental block erasure, byte writing, or lock-bit
configuration during power transitions. Upon power-
up, the device is indifferent as to which power
supply (V
circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for V
active. Since both WE# and CE# must be low for a
command write, driving either input signal to V
inhibit writes. The CUI’s
sequence architecture provides an added level of
protection against data alteration.
In-system block lock and unlock renders additional
protection during power-up by prohibiting block
erase and program operations. The device is
disabled while RP# = V
inputs state.
V
IH
V
Boards
V
Power-Up/Down Protection
PP
range
PP
CC
or V
CC
PP
, V
28F004S3/28F008S3/28F016S3
or V
Trace on Printed Circuit
pin supplies the memory cell current
IL
voltages above V
HH
PP
during block erase, program, or
. If V
PP
CC
(V
, RP# Transitions
or V
) powers-up first. Internal
CC2
PP
IL
CC
PP
error is detected, status
regardless of its control
PP
and
fall outside of a valid
two-step command
supply traces and
voltage spikes and
PP
LKO
power supply
V
when V
PPH1/2
)
IH
PP
will
27
CC
or
is