TB28F004S3-150 Intel, TB28F004S3-150 Datasheet - Page 36

no-image

TB28F004S3-150

Manufacturer Part Number
TB28F004S3-150
Description
Manufacturer
Intel
Datasheet

Specifications of TB28F004S3-150

Density
4Mb
Access Time (max)
150ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
19b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
SOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
512K
Supply Current
18mA
Mounting
Surface Mount
Pin Count
44
Lead Free Status / Rohs Status
Not Compliant
28F004S3/28F008S3/28F016S3
6.6
T
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
36
A
W10 t
W11 t
W12 t
W13 t
W14 t
W15 t
W1
W2
W3
W4
W5
W6
W7
W8
W9
= 0 °C to +70 °C
#
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics—Read-Only Operations .
A write operation can be initiated and terminated with either CE# or WE#.
Sampled, not 100% tested.
Refer to Table 3 for valid A
V
lock-bit configuration success (SR.1/3/4/5 = 0).
See Ordering Information for device speeds (valid operational combinations).
Write pulse width (t
(whichever goes high first). Hence, t
WE# pulse width requirement decreases to t
Block erase, program, and lock-bit configuration with V
Write pulse width high (t
(whichever goes low last). Hence, t
PP
should be held at V
t
t
t
t
t
t
t
t
t
AC Characteristics—Write Operations
PHWL
ELWL
WP
DVWH
AVWH
WHEH
WHDX
WHAX
WPH
PHHWH
VPWH
WHRL
WHGL
QVPH
QVVL
Sym
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
PHEL
AVEH
EHAX
(t
VPEH
EHRL
EHGL
DVEH
EHWH
EHDX
PHHEH
WP
)
)
)
)
)
)
)
)
)
)
) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
) RP# V
PPH1/2
WPH
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
Write Pulse Width
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
Write Pulse Width High
V
WE# (CE#) High to RY/BY# Going Low
Write Recovery before Read
RP# V
V
IN
PP
PP
) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
and D
Versions
(and if necessary RP# should be held at V
Setup to WE# (CE#) Going High
Hold from Valid SRD, RY/BY# High
HH
HH
WPH
IN
WP
Setup to WE# (CE#) Going High
Hold from Valid SRD, RY/BY# High
for block erase, program, or lock-bit configuration.
= t
= t
(4)
WLWH
WHWL
WP
- 20 ns.
= t
= t
Parameter
ELEH
EHEL
CC
= t
= t
WLEH
WHEL
2.7 V should not be attempted.
= t
= t
(1, 2)
ELWH
EHWL
. If CE# is driven low 10 ns before WE# going low,
.
—Commercial Temperature
HH
) until determination of block erase, program, or
2.7V 3.6V V
3.3V ± 0.3V,
Notes
3,5,8
3,5,8
3,8
3,8
3
7
7
4
4
9
8
PRELIMINARY
CC
Valid for All
Min
100
100
70
50
50
25
1
0
0
5
5
0
0
0
Speeds
Max
90
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for TB28F004S3-150